ddr_tx_ucf.ucf

FPGA芯片与ADI公司的AD9779之间的通信

net DATA_TX_P_0<0> loc=AU42;  #DAC1_D1_P  
net DATA_TX_P_0<1> loc=AT41;  #DAC1_D2_P  
net DATA_TX_P_0<2> loc=AR42;  #DAC1_D3_P  
net DATA_TX_P_0<3> loc=AP42;  #DAC1_D4_P  
net DATA_TX_P_0<4> loc=AM41;  #DAC1_D5_P  
net DATA_TX_P_0<5> loc=AL42;  #DAC1_D6_P  
net DATA_TX_P_0<6> loc=AL41;  #DAC1_D7_P  
net DATA_TX_P_0<7> loc=AJ42;  #DAC1_D8_P  
net DATA_TX_P_0<8> loc=AH40;  #DAC1_D9_P  
net DATA_TX_P_0<9> loc=AG42;  #DAC1_D10_P  
net DATA_TX_P_0<10> loc=AF40; #DAC1_D11_P  
net DATA_TX_P_0<11> loc=AF41; #DAC1_D12_P  
net DATA_TX_P_0<12> loc=AE42; #DAC1_D13_P  
net DATA_TX_P_0<13> loc=AC41; #DAC1_D14_P  
net DATA_TX_P_0<14> loc=AC40; #DAC1_D15_P  
net DATA_TX_P_0<15> loc=AB41; #DAC1_D16_P  

net DATA_TX_N_0<0> loc=AV41; #DAC1_D1_N  
net DATA_TX_N_0<1> loc=AU41; #DAC1_D2_N  
net DATA_TX_N_0<2> loc=AT42; #DAC1_D3_N  
net DATA_TX_N_0<3> loc=AP41; #DAC1_D4_N  
net DATA_TX_N_0<4> loc=AN41; #DAC1_D5_N  
net DATA_TX_N_0<5> loc=AM42; #DAC1_D6_N  
net DATA_TX_N_0<6> loc=AK42; #DAC1_D7_N  
net DATA_TX_N_0<7> loc=AJ41; #DAC1_D8_N  
net DATA_TX_N_0<8> loc=AJ40; #DAC1_D9_N  
net DATA_TX_N_0<9> loc=AH41; #DAC1_D10_N  
net DATA_TX_N_0<10> loc=AG41; #DAC1_D11_N  
net DATA_TX_N_0<11> loc=AF42; #DAC1_D12_N  
net DATA_TX_N_0<12> loc=AD41; #DAC1_D13_N  
net DATA_TX_N_0<13> loc=AD42; #DAC1_D14_N  
net DATA_TX_N_0<14> loc=AC39; #DAC1_D15_N  
net DATA_TX_N_0<15> loc=AB42; #DAC1_D16_N  

###############################################################

net DATA_TX_P_1<0> loc=AN40;  #DAC2_D1_P  
net DATA_TX_P_1<1> loc=AN39;  #DAC2_D2_P  
net DATA_TX_P_1<2> loc=AN38;  #DAC2_D3_P  
net DATA_TX_P_1<3> loc=AL39;  #DAC2_D4_P  
net DATA_TX_P_1<4> loc=AM37;  #DAC2_D5_P  
net DATA_TX_P_1<5> loc=AK38;  #DAC2_D6_P  
net DATA_TX_P_1<6> loc=AJ38;  #DAC2_D7_P  
net DATA_TX_P_1<7> loc=AJ37;  #DAC2_D8_P  
net DATA_TX_P_1<8> loc=AF39;  #DAC2_D9_P  
net DATA_TX_P_1<9> loc=AG37;  #DAC2_D10_P  
net DATA_TX_P_1<10> loc=AE39; #DAC2_D11_P  
net DATA_TX_P_1<11> loc=AE37; #DAC2_D12_P  
net DATA_TX_P_1<12> loc=AD36; #DAC2_D13_P  
net DATA_TX_P_1<13> loc=AC36; #DAC2_D14_P  
net DATA_TX_P_1<14> loc=AC35; #DAC2_D15_P  
net DATA_TX_P_1<15> loc=AB34; #DAC2_D16_P  

net DATA_TX_N_1<0> loc=AP40;  #DAC2_D1_N  
net DATA_TX_N_1<1> loc=AP38;  #DAC2_D2_N  
net DATA_TX_N_1<2> loc=AM38;  #DAC2_D3_N  
net DATA_TX_N_1<3> loc=AM39;  #DAC2_D4_N  
net DATA_TX_N_1<4> loc=AL37;  #DAC2_D5_N  
net DATA_TX_N_1<5> loc=AK37;  #DAC2_D6_N  
net DATA_TX_N_1<6> loc=AK39;  #DAC2_D7_N  
net DATA_TX_N_1<7> loc=AH38;  #DAC2_D8_N  
net DATA_TX_N_1<8> loc=AG38;  #DAC2_D9_N  
net DATA_TX_N_1<9> loc=AF37;  #DAC2_D10_N  
net DATA_TX_N_1<10> loc=AE38; #DAC2_D11_N  
net DATA_TX_N_1<11> loc=AD38; #DAC2_D12_N  
net DATA_TX_N_1<12> loc=AD37; #DAC2_D13_N  
net DATA_TX_N_1<13> loc=AD35; #DAC2_D14_N  
net DATA_TX_N_1<14> loc=AB36; #DAC2_D15_N  
net DATA_TX_N_1<15> loc=AC34; #DAC2_D16_N  

###############################################################

net DATA_TX_P_2<0> loc=AA42;  #DAC3_D1_P  
net DATA_TX_P_2<1> loc=W40;  #DAC3_D2_P  
net DATA_TX_P_2<2> loc=W42;  #DAC3_D3_P  
net DATA_TX_P_2<3> loc=V40;  #DAC3_D4_P  
net DATA_TX_P_2<4> loc=U42;  #DAC3_D5_P  
net DATA_TX_P_2<5> loc=T42;  #DAC3_D6_P  
net DATA_TX_P_2<6> loc=T40;  #DAC3_D7_P  
net DATA_TX_P_2<7> loc=P41;  #DAC3_D8_P  
net DATA_TX_P_2<8> loc=N40;  #DAC3_D9_P  
net DATA_TX_P_2<9> loc=M42;  #DAC3_D10_P  
net DATA_TX_P_2<10> loc=L42; #DAC3_D11_P  
net DATA_TX_P_2<11> loc=L40; #DAC3_D12_P  
net DATA_TX_P_2<12> loc=J42; #DAC3_D13_P  
net DATA_TX_P_2<13> loc=H41; #DAC3_D14_P  
net DATA_TX_P_2<14> loc=F42; #DAC3_D15_P  
net DATA_TX_P_2<15> loc=F41; #DAC3_D16_P  

net DATA_TX_N_2<0> loc=AA41;  #DAC3_D1_N  
net DATA_TX_N_2<1> loc=Y40;  #DAC3_D2_N  
net DATA_TX_N_2<2> loc=Y42;  #DAC3_D3_N  
net DATA_TX_N_2<3> loc=W41;  #DAC3_D4_N  
net DATA_TX_N_2<4> loc=V41;  #DAC3_D5_N  
net DATA_TX_N_2<5> loc=U41;  #DAC3_D6_N  
net DATA_TX_N_2<6> loc=T41;  #DAC3_D7_N  
net DATA_TX_N_2<7> loc=R40;  #DAC3_D8_N  
net DATA_TX_N_2<8> loc=P40;  #DAC3_D9_N  
net DATA_TX_N_2<9> loc=N41;  #DAC3_D10_N  
net DATA_TX_N_2<10> loc=M41; #DAC3_D11_N  
net DATA_TX_N_2<11> loc=L41; #DAC3_D12_N  
net DATA_TX_N_2<12> loc=K42; #DAC3_D13_N  
net DATA_TX_N_2<13> loc=J41; #DAC3_D14_N  
net DATA_TX_N_2<14> loc=G42; #DAC3_D15_N  
net DATA_TX_N_2<15> loc=G41; #DAC3_D16_N  

###############################################################

net DATA_TX_P_3<0> loc=AA35;  #DAC4_D1_P  
net DATA_TX_P_3<1> loc=AA34;  #DAC4_D2_P  
net DATA_TX_P_3<2> loc=Y35;  #DAC4_D3_P  
net DATA_TX_P_3<3> loc=W36;  #DAC4_D4_P  
net DATA_TX_P_3<4> loc=V39;  #DAC4_D5_P  
net DATA_TX_P_3<5> loc=T39;  #DAC4_D6_P  
net DATA_TX_P_3<6> loc=T37;  #DAC4_D7_P  
net DATA_TX_P_3<7> loc=R39;  #DAC4_D8_P  
net DATA_TX_P_3<8> loc=R37;  #DAC4_D9_P  
net DATA_TX_P_3<9> loc=P38;  #DAC4_D10_P  
net DATA_TX_P_3<10> loc=N39; #DAC4_D11_P  
net DATA_TX_P_3<11> loc=M38; #DAC4_D12_P  
net DATA_TX_P_3<12> loc=H38; #DAC4_D13_P  
net DATA_TX_P_3<13> loc=G38; #DAC4_D14_P  
net DATA_TX_P_3<14> loc=F39; #DAC4_D15_P  
net DATA_TX_P_3<15> loc=E39; #DAC4_D16_P  

net DATA_TX_N_3<0> loc=AA36; #DAC4_D1_N  
net DATA_TX_N_3<1> loc=Y34; #DAC4_D2_N  
net DATA_TX_N_3<2> loc=W35; #DAC4_D3_N  
net DATA_TX_N_3<3> loc=W37; #DAC4_D4_N  
net DATA_TX_N_3<4> loc=W38; #DAC4_D5_N  
net DATA_TX_N_3<5> loc=U39; #DAC4_D6_N  
net DATA_TX_N_3<6> loc=U38; #DAC4_D7_N  
net DATA_TX_N_3<7> loc=R38; #DAC4_D8_N  
net DATA_TX_N_3<8> loc=P37; #DAC4_D9_N  
net DATA_TX_N_3<9> loc=N38; #DAC4_D10_N  
net DATA_TX_N_3<10> loc=M39; #DAC4_D11_N  
net DATA_TX_N_3<11> loc=L39; #DAC4_D12_N  
net DATA_TX_N_3<12> loc=H39; #DAC4_D13_N  
net DATA_TX_N_3<13> loc=G39; #DAC4_D14_N  
net DATA_TX_N_3<14> loc=F40; #DAC4_D15_N  
net DATA_TX_N_3<15> loc=E40; #DAC4_D16_N 

###############################################################
		
net CLOCK_TX_P_0 loc=AE40; #DAC1_DATA_CLK_P  
net CLOCK_TX_N_0 loc=AD40; #DAC1_DATA_CLK_N  
net CLOCK_TX_P_1 loc=AT39; #DAC2_DATA_CLK_P  
net CLOCK_TX_N_1 loc=AR39; #DAC2_DATA_CLK_N  
net CLOCK_TX_P_2 loc=AA40; #DAC3_DATA_CLK_P  
net CLOCK_TX_N_2 loc=AA39; #DAC3_DATA_CLK_N  
net CLOCK_TX_P_3 loc=K40; #DAC4_DATA_CLK_P  
net CLOCK_TX_N_3 loc=K39; #DAC4_DATA_CLK_N  

#########################################################

net dbg_clk_122 LOC=N28; 
net dbg_clk_30 LOC=N29;   
net RESET_N loc=K28;     #on mother board

net USER_CLK loc=M26;     #30.72MHz From CPLD
net CLK_50M loc=K29;      #50MHz

NET "CLK_50M" TNM_NET =  "CLK_50M";
TIMESPEC "TS_CLK_50M" = PERIOD "CLK_50M" 20 ns HIGH 50 %;		

NET "USER_CLK" TNM_NET =  "USER_CLK";
TIMESPEC "TS_USER_CLK" = PERIOD "USER_CLK" 30 ns HIGH 50 %;



#################################################################################
#################################################################################
#################################################################################
###############                                            ######################      
###############                   李林军的DAC板测试UCF         ######################
###############                                            ######################
#################################################################################
#################################################################################
#################################################################################


net DATA_TX_P_0<0> loc=AN34;  #DAC1_D1_P  --
net DATA_TX_P_0<1> loc=AN32;  #DAC1_D2_P  --
net DATA_TX_P_0<2> loc=AL34;  #DAC1_D3_P  --
net DATA_TX_P_0<3> loc=AM33;  #DAC1_D4_P  --
net DATA_TX_P_0<4> loc=AK34;  #DAC1_D5_P  --
net DATA_TX_P_0<5> loc=AJ32;  #DAC1_D6_P  
net DATA_TX_P_0<6> loc=AH34;  #DAC1_D7_P  
net DATA_TX_P_0<7> loc=AG32;  #DAC1_D8_P  
net DATA_TX_P_0<8> loc=AC34;  #DAC1_D9_P  
net DATA_TX_P_0<9> loc=AC33;  #DAC1_D10_P  
net DATA_TX_P_0<10> loc=AA34; #DAC1_D11_P  
net DATA_TX_P_0<11> loc=AF41; #DAC1_D12_P  
net DATA_TX_P_0<12> loc=AE42; #DAC1_D13_P  
net DATA_TX_P_0<13> loc=AC41; #DAC1_D14_P  
net DATA_TX_P_0<14> loc=AC40; #DAC1_D15_P  
net DATA_TX_P_0<15> loc=AB41; #DAC1_D16_P  

net DATA_TX_N_0<0> loc=AN33; #DAC1_D1_N  --
net DATA_TX_N_0<1> loc=AP32; #DAC1_D2_N  --
net DATA_TX_N_0<2> loc=AL33; #DAC1_D3_N  --
net DATA_TX_N_0<3> loc=AM32; #DAC1_D4_N  --
net DATA_TX_N_0<4> loc=AK33; #DAC1_D5_N  --
net DATA_TX_N_0<5> loc=AK32; #DAC1_D6_N  
net DATA_TX_N_0<6> loc=AJ34; #DAC1_D7_N  
net DATA_TX_N_0<7> loc=AH32; #DAC1_D8_N  
net DATA_TX_N_0<8> loc=AD34; #DAC1_D9_N  
net DATA_TX_N_0<9> loc=AB33; #DAC1_D10_N  
net DATA_TX_N_0<10> loc=AG41; #DAC1_D11_N  
net DATA_TX_N_0<11> loc=AF42; #DAC1_D12_N  
net DATA_TX_N_0<12> loc=AD41; #DAC1_D13_N  
net DATA_TX_N_0<13> loc=AD42; #DAC1_D14_N  
net DATA_TX_N_0<14> loc=AC39; #DAC1_D15_N  
net DATA_TX_N_0<15> loc=AB42; #DAC1_D16_N  

###############################################################

net DATA_TX_P_1<0> loc=AN40;  #DAC2_D1_P  
net DATA_TX_P_1<1> loc=AN39;  #DAC2_D2_P  
net DATA_TX_P_1<2> loc=AN38;  #DAC2_D3_P  
net DATA_TX_P_1<3> loc=AL39;  #DAC2_D4_P  
net DATA_TX_P_1<4> loc=AM37;  #DAC2_D5_P  
net DATA_TX_P_1<5> loc=AK38;  #DAC2_D6_P  
net DATA_TX_P_1<6> loc=AJ38;  #DAC2_D7_P  
net DATA_TX_P_1<7> loc=AJ37;  #DAC2_D8_P  
net DATA_TX_P_1<8> loc=AF39;  #DAC2_D9_P  
net DATA_TX_P_1<9> loc=AG37;  #DAC2_D10_P  
net DATA_TX_P_1<10> loc=AE39; #DAC2_D11_P  
net DATA_TX_P_1<11> loc=AE37; #DAC2_D12_P  
net DATA_TX_P_1<12> loc=AD36; #DAC2_D13_P  
net DATA_TX_P_1<13> loc=AC36; #DAC2_D14_P  
net DATA_TX_P_1<14> loc=AC35; #DAC2_D15_P  
net DATA_TX_P_1<15> loc=AB34; #DAC2_D16_P  

net DATA_TX_N_1<0> loc=AP40;  #DAC2_D1_N  
net DATA_TX_N_1<1> loc=AP38;  #DAC2_D2_N  
net DATA_TX_N_1<2> loc=AM38;  #DAC2_D3_N  
net DATA_TX_N_1<3> loc=AM39;  #DAC2_D4_N  
net DATA_TX_N_1<4> loc=AL37;  #DAC2_D5_N  
net DATA_TX_N_1<5> loc=AK37;  #DAC2_D6_N  
net DATA_TX_N_1<6> loc=AK39;  #DAC2_D7_N  
net DATA_TX_N_1<7> loc=AH38;  #DAC2_D8_N  
net DATA_TX_N_1<8> loc=AG38;  #DAC2_D9_N  
net DATA_TX_N_1<9> loc=AF37;  #DAC2_D10_N  
net DATA_TX_N_1<10> loc=AE38; #DAC2_D11_N  
net DATA_TX_N_1<11> loc=AD38; #DAC2_D12_N  
net DATA_TX_N_1<12> loc=AD37; #DAC2_D13_N  
net DATA_TX_N_1<13> loc=AD35; #DAC2_D14_N  
net DATA_TX_N_1<14> loc=AB36; #DAC2_D15_N  
net DATA_TX_N_1<15> loc=AC34; #DAC2_D16_N  

###############################################################

net DATA_TX_P_2<0> loc=AA42;  #DAC3_D1_P  
net DATA_TX_P_2<1> loc=W40;  #DAC3_D2_P  
net DATA_TX_P_2<2> loc=W42;  #DAC3_D3_P  
net DATA_TX_P_2<3> loc=V40;  #DAC3_D4_P  
net DATA_TX_P_2<4> loc=U42;  #DAC3_D5_P  
net DATA_TX_P_2<5> loc=T42;  #DAC3_D6_P  
net DATA_TX_P_2<6> loc=T40;  #DAC3_D7_P  
net DATA_TX_P_2<7> loc=P41;  #DAC3_D8_P  
net DATA_TX_P_2<8> loc=N40;  #DAC3_D9_P  
net DATA_TX_P_2<9> loc=M42;  #DAC3_D10_P  
net DATA_TX_P_2<10> loc=L42; #DAC3_D11_P  
net DATA_TX_P_2<11> loc=L40; #DAC3_D12_P  
net DATA_TX_P_2<12> loc=J42; #DAC3_D13_P  
net DATA_TX_P_2<13> loc=H41; #DAC3_D14_P  
net DATA_TX_P_2<14> loc=F42; #DAC3_D15_P  
net DATA_TX_P_2<15> loc=F41; #DAC3_D16_P  

net DATA_TX_N_2<0> loc=AA41;  #DAC3_D1_N  
net DATA_TX_N_2<1> loc=Y40;  #DAC3_D2_N  
net DATA_TX_N_2<2> loc=Y42;  #DAC3_D3_N  
net DATA_TX_N_2<3> loc=W41;  #DAC3_D4_N  
net DATA_TX_N_2<4> loc=V41;  #DAC3_D5_N  
net DATA_TX_N_2<5> loc=U41;  #DAC3_D6_N  
net DATA_TX_N_2<6> loc=T41;  #DAC3_D7_N  
net DATA_TX_N_2<7> loc=R40;  #DAC3_D8_N  
net DATA_TX_N_2<8> loc=P40;  #DAC3_D9_N  
net DATA_TX_N_2<9> loc=N41;  #DAC3_D10_N  
net DATA_TX_N_2<10> loc=M41; #DAC3_D11_N  
net DATA_TX_N_2<11> loc=L41; #DAC3_D12_N  
net DATA_TX_N_2<12> loc=K42; #DAC3_D13_N  
net DATA_TX_N_2<13> loc=J41; #DAC3_D14_N  
net DATA_TX_N_2<14> loc=G42; #DAC3_D15_N  
net DATA_TX_N_2<15> loc=G41; #DAC3_D16_N  

###############################################################

net DATA_TX_P_3<0> loc=AA35;  #DAC4_D1_P  
net DATA_TX_P_3<1> loc=AA34;  #DAC4_D2_P  
net DATA_TX_P_3<2> loc=Y35;  #DAC4_D3_P  
net DATA_TX_P_3<3> loc=W36;  #DAC4_D4_P  
net DATA_TX_P_3<4> loc=V39;  #DAC4_D5_P  
net DATA_TX_P_3<5> loc=T39;  #DAC4_D6_P  
net DATA_TX_P_3<6> loc=T37;  #DAC4_D7_P  
net DATA_TX_P_3<7> loc=R39;  #DAC4_D8_P  
net DATA_TX_P_3<8> loc=R37;  #DAC4_D9_P  
net DATA_TX_P_3<9> loc=P38;  #DAC4_D10_P  
net DATA_TX_P_3<10> loc=N39; #DAC4_D11_P  
net DATA_TX_P_3<11> loc=M38; #DAC4_D12_P  
net DATA_TX_P_3<12> loc=H38; #DAC4_D13_P  
net DATA_TX_P_3<13> loc=G38; #DAC4_D14_P  
net DATA_TX_P_3<14> loc=F39; #DAC4_D15_P  
net DATA_TX_P_3<15> loc=E39; #DAC4_D16_P  

net DATA_TX_N_3<0> loc=AA36; #DAC4_D1_N  
net DATA_TX_N_3<1> loc=Y34; #DAC4_D2_N  
net DATA_TX_N_3<2> loc=W35; #DAC4_D3_N  
net DATA_TX_N_3<3> loc=W37; #DAC4_D4_N  
net DATA_TX_N_3<4> loc=W38; #DAC4_D5_N  
net DATA_TX_N_3<5> loc=U39; #DAC4_D6_N  
net DATA_TX_N_3<6> loc=U38; #DAC4_D7_N  
net DATA_TX_N_3<7> loc=R38; #DAC4_D8_N  
net DATA_TX_N_3<8> loc=P37; #DAC4_D9_N  
net DATA_TX_N_3<9> loc=N38; #DAC4_D10_N  
net DATA_TX_N_3<10> loc=M39; #DAC4_D11_N  
net DATA_TX_N_3<11> loc=L39; #DAC4_D12_N  
net DATA_TX_N_3<12> loc=H39; #DAC4_D13_N  
net DATA_TX_N_3<13> loc=G39; #DAC4_D14_N  
net DATA_TX_N_3<14> loc=F40; #DAC4_D15_N  
net DATA_TX_N_3<15> loc=E40; #DAC4_D16_N 

###############################################################
		
net CLOCK_TX_P_0 loc=AE40; #DAC1_DATA_CLK_P  
net CLOCK_TX_N_0 loc=AD40; #DAC1_DATA_CLK_N  
net CLOCK_TX_P_1 loc=AT39; #DAC2_DATA_CLK_P  
net CLOCK_TX_N_1 loc=AR39; #DAC2_DATA_CLK_N  
net CLOCK_TX_P_2 loc=AA40; #DAC3_DATA_CLK_P  
net CLOCK_TX_N_2 loc=AA39; #DAC3_DATA_CLK_N  
net CLOCK_TX_P_3 loc=K40; #DAC4_DATA_CLK_P  
net CLOCK_TX_N_3 loc=K39; #DAC4_DATA_CLK_N