ddr_tx_test.syr

FPGA芯片与ADI公司的AD9779之间的通信

Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-----------------------------+-------+
Clock Signal                       | Clock buffer(FF name)       | Load  |
-----------------------------------+-----------------------------+-------+
u_PLL_tx/CLKOUT0_BUF               | BUFG                        | 196   |
CLK_50M                            | BUFGP                       | 9     |
u_DDR_TX_TOP/ClkCnt_8              | NONE(u_DDR_TX_TOP/RESET_r_9)| 10    |
-----------------------------------+-----------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------+------------------------+-------+
Control Signal                         | Buffer(FF name)        | Load  |
---------------------------------------+------------------------+-------+
RESET_SYS_N_inv(u_DDR_TX_TOP/reset_i:O)| NONE(DATA_TX_USER_2_18)| 128   |
---------------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 2.143ns (Maximum Frequency: 466.636MHz)
   Minimum input arrival time before clock: 1.727ns
   Maximum output required time after clock: 4.910ns
   Maximum combinational path delay: 3.611ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'u_PLL_tx/CLKOUT0_BUF'
  Clock period: 2.143ns (frequency: 466.636MHz)
  Total number of paths / destination ports: 1216 / 256
-------------------------------------------------------------------------
Delay:               2.143ns (Levels of Logic = 17)
  Source:            DATA_TX_USER_0_16 (FF)
  Destination:       DATA_TX_USER_0_31 (FF)
  Source Clock:      u_PLL_tx/CLKOUT0_BUF rising
  Destination Clock: u_PLL_tx/CLKOUT0_BUF rising

  Data Path: DATA_TX_USER_0_16 to DATA_TX_USER_0_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              2   0.471   0.341  DATA_TX_USER_0_16 (DATA_TX_USER_0_16)
     INV:I->O              1   0.238   0.000  Madd__add0001_lut<0>_INV_0 (Madd__add0001_lut<0>)
     MUXCY:S->O            1   0.372   0.000  Madd__add0001_cy<0> (Madd__add0001_cy<0>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<1> (Madd__add0001_cy<1>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<2> (Madd__add0001_cy<2>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<3> (Madd__add0001_cy<3>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<4> (Madd__add0001_cy<4>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<5> (Madd__add0001_cy<5>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<6> (Madd__add0001_cy<6>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<7> (Madd__add0001_cy<7>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<8> (Madd__add0001_cy<8>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<9> (Madd__add0001_cy<9>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<10> (Madd__add0001_cy<10>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<11> (Madd__add0001_cy<11>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<12> (Madd__add0001_cy<12>)
     MUXCY:CI->O           1   0.026   0.000  Madd__add0001_cy<13> (Madd__add0001_cy<13>)
     MUXCY:CI->O           0   0.026   0.000  Madd__add0001_cy<14> (Madd__add0001_cy<14>)
     XORCY:CI->O           1   0.357   0.000  Madd__add0001_xor<15> (_add0001<15>)
     FDP:D                    -0.018          DATA_TX_USER_0_31
    ----------------------------------------
    Total                      2.143ns (1.802ns logic, 0.341ns route)
                                       (84.1% logic, 15.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK_50M'
  Clock period: 1.956ns (frequency: 511.247MHz)
  Total number of paths / destination ports: 45 / 9
-------------------------------------------------------------------------
Delay:               1.956ns (Levels of Logic = 10)
  Source:            u_DDR_TX_TOP/ClkCnt_0 (FF)
  Destination:       u_DDR_TX_TOP/ClkCnt_8 (FF)
  Source Clock:      CLK_50M rising
  Destination Clock: CLK_50M rising

  Data Path: u_DDR_TX_TOP/ClkCnt_0 to u_DDR_TX_TOP/ClkCnt_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.471   0.336  u_DDR_TX_TOP/ClkCnt_0 (u_DDR_TX_TOP/ClkCnt_0)
     INV:I->O              1   0.238   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_lut<0>_INV_0 (u_DDR_TX_TOP/Mcount_ClkCnt_lut<0>)
     MUXCY:S->O            1   0.372   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<0> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<0>)
     MUXCY:CI->O           1   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<1> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<1>)
     MUXCY:CI->O           1   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<2> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<2>)
     MUXCY:CI->O           1   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<3> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>)
     MUXCY:CI->O           1   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<4> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<4>)
     MUXCY:CI->O           1   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<5> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<5>)
     MUXCY:CI->O           1   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<6> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<6>)
     MUXCY:CI->O           0   0.026   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_cy<7> (u_DDR_TX_TOP/Mcount_ClkCnt_cy<7>)
     XORCY:CI->O           1   0.357   0.000  u_DDR_TX_TOP/Mcount_ClkCnt_xor<8> (u_DDR_TX_TOP/Result<8>)
     FD:D                     -0.018          u_DDR_TX_TOP/ClkCnt_8
    ----------------------------------------
    Total                      1.956ns (1.620ns logic, 0.336ns route)
                                       (82.8% logic, 17.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u_DDR_TX_TOP/ClkCnt_8'
  Clock period: 0.818ns (frequency: 1222.494MHz)
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Delay:               0.818ns (Levels of Logic = 0)
  Source:            u_DDR_TX_TOP/RESET_r_8 (FF)
  Destination:       u_DDR_TX_TOP/RESET_r_9 (FF)
  Source Clock:      u_DDR_TX_TOP/ClkCnt_8 rising
  Destination Clock: u_DDR_TX_TOP/ClkCnt_8 rising

  Data Path: u_DDR_TX_TOP/RESET_r_8 to u_DDR_TX_TOP/RESET_r_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.471   0.347  u_DDR_TX_TOP/RESET_r_8 (u_DDR_TX_TOP/RESET_r_8)
     FD:D                     -0.018          u_DDR_TX_TOP/RESET_r_9
    ----------------------------------------
    Total                      0.818ns (0.471ns logic, 0.347ns route)
                                       (57.6% logic, 42.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'u_DDR_TX_TOP/ClkCnt_8'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.727ns (Levels of Logic = 1)
  Source:            RESET_N (PAD)
  Destination:       u_DDR_TX_TOP/RESET_r_0 (FF)
  Destination Clock: u_DDR_TX_TOP/ClkCnt_8 rising

  Data Path: RESET_N to u_DDR_TX_TOP/RESET_r_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.818   0.336  RESET_N_IBUF (RESET_N_IBUF)
     FDR:R                     0.573          u_DDR_TX_TOP/RESET_r_0
    ----------------------------------------
    Total                      1.727ns (1.391ns logic, 0.336ns route)
                                       (80.5% logic, 19.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u_PLL_tx/CLKOUT0_BUF'
  Total number of paths / destination ports: 136 / 136
-------------------------------------------------------------------------
Offset:              2.429ns (Levels of Logic = 1)
  Source:            u_DDR_TX_TOP/u_DDR_TX_0/u_ODDR_clk (FF)
  Destination:       CLOCK_TX_N_0 (PAD)
  Source Clock:      u_PLL_tx/CLKOUT0_BUF rising

  Data Path: u_DDR_TX_TOP/u_DDR_TX_0/u_ODDR_clk to CLOCK_TX_N_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     ODDR:C->Q             1   0.607   0.336  u_DDR_TX_TOP/u_DDR_TX_0/u_ODDR_clk (u_DDR_TX_TOP/u_DDR_TX_0/clk_tx_ds)
     OBUFDS_LVDSEXT_25:I->O        1.486          u_DDR_TX_TOP/u_DDR_TX_0/u_OBUFDS_clk (CLOCK_TX_P_0)
    ----------------------------------------
    Total                      2.429ns (2.093ns logic, 0.336ns route)
                                       (86.2% logic, 13.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u_DDR_TX_TOP/ClkCnt_8'
  Total number of paths / destination ports: 20 / 2
-------------------------------------------------------------------------
Offset:              4.910ns (Levels of Logic = 3)
  Source:            u_DDR_TX_TOP/RESET_r_3 (FF)
  Destination:       RESET_SYS_N (PAD)
  Source Clock:      u_DDR_TX_TOP/ClkCnt_8 rising

  Data Path: u_DDR_TX_TOP/RESET_r_3 to RESET_SYS_N
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.471   0.978  u_DDR_TX_TOP/RESET_r_3 (u_DDR_TX_TOP/RESET_r_3)
     LUT5:I0->O            2   0.094   0.485  u_DDR_TX_TOP/reset_i_SW0 (N0)
     LUT6:I5->O            1   0.094   0.336  u_DDR_TX_TOP/RESET_SYS_N1 (RESET_SYS_N_OBUF)
     OBUF:I->O                 2.452          RESET_SYS_N_OBUF (RESET_SYS_N)
    ----------------------------------------
    Total                      4.910ns (3.111ns logic, 1.799ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Delay:               3.611ns (Levels of Logic = 2)
  Source:            USER_CLK (PAD)
  Destination:       dbg_clk_30 (PAD)

  Data Path: USER_CLK to dbg_clk_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUFG:I->O            2   0.818   0.341  u_PLL_tx/CLKIN1_IBUFG_INST (dbg_clk_30_OBUF)
     OBUF:I->O                 2.452          dbg_clk_30_OBUF (dbg_clk_30)
    ----------------------------------------
    Total                      3.611ns (3.270ns logic, 0.341ns route)
                                       (90.6% logic, 9.4% route)

=========================================================================


Total REAL time to Xst completion: 89.00 secs
Total CPU time to Xst completion: 88.78 secs
 
--> 

Total memory usage is 387020 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  179 (   0 filtered)
Number of infos    :    1 (   0 filtered)