ddr_tx_test.syr

FPGA芯片与ADI公司的AD9779之间的通信

    Set user-defined property "CLKOUT5_DESKEW_ADJUST =  NONE" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "CLKOUT5_DIVIDE =  8" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "CLKOUT5_DUTY_CYCLE =  0.5000000000000000" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "CLKOUT5_PHASE =  0.0000000000000000" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "COMPENSATION =  SYSTEM_SYNCHRONOUS" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "DIVCLK_DIVIDE =  1" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "EN_REL =  FALSE" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "PLL_PMCD_MODE =  FALSE" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "REF_JITTER =  0.0050000000000000" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "RESET_ON_LOSS_OF_LOCK =  FALSE" for instance <PLL_ADV_INST> in unit <PLL_tx>.
    Set user-defined property "RST_DEASSERT_CLK =  CLKIN1" for instance <PLL_ADV_INST> in unit <PLL_tx>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <PLL_tx>.
    Related source file is "PLL_tx.v".
Unit <PLL_tx> synthesized.


Synthesizing Unit <DDR_TX>.
    Related source file is "DDR_TX.v".
WARNING:Xst:1780 - Signal <data_tx_ddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <DDR_TX> synthesized.


Synthesizing Unit <DDR_TX_TOP>.
    Related source file is "DDR_TX_TOP.v".
    Found 9-bit up counter for signal <ClkCnt>.
    Found 10-bit register for signal <RESET_r>.
    Summary:
	inferred   1 Counter(s).
	inferred  10 D-type flip-flop(s).
Unit <DDR_TX_TOP> synthesized.


Synthesizing Unit <DDR_TX_TEST>.
    Related source file is "DDR_TX_TEST.v".
    Found 16-bit adder for signal <$add0000> created at line 70.
    Found 16-bit adder for signal <$add0001> created at line 71.
    Found 16-bit adder for signal <$add0002> created at line 73.
    Found 16-bit adder for signal <$add0003> created at line 74.
    Found 16-bit adder for signal <$add0004> created at line 76.
    Found 16-bit adder for signal <$add0005> created at line 77.
    Found 16-bit adder for signal <$add0006> created at line 79.
    Found 16-bit adder for signal <$add0007> created at line 80.
    Found 32-bit register for signal <DATA_TX_USER_0>.
    Found 32-bit register for signal <DATA_TX_USER_1>.
    Found 32-bit register for signal <DATA_TX_USER_2>.
    Found 32-bit register for signal <DATA_TX_USER_3>.
    Summary:
	inferred 128 D-type flip-flop(s).
	inferred   8 Adder/Subtractor(s).
Unit <DDR_TX_TEST> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 8
 16-bit adder                                          : 8
# Counters                                             : 1
 9-bit up counter                                      : 1
# Registers                                            : 129
 1-bit register                                        : 128
 10-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '5vfx130t.nph' in environment E:\FPGA\Xilinx\10.1\ISE.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 8
 16-bit adder                                          : 8
# Counters                                             : 1
 9-bit up counter                                      : 1
# Registers                                            : 138
 Flip-Flops                                            : 138

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance u_ODDR_clk in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[0].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[1].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[2].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[3].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[4].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[5].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[6].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[7].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[8].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[9].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[10].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[11].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[12].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[13].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[14].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[15].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance u_ODDR_clk in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[0].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[1].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[2].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[3].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[4].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[5].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[6].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[7].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[8].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[9].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[10].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[11].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[12].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[13].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[14].u_ODDR_data in unit DDR_TX is not supported
WARNING:Xst:1902 - Value 00000000 for attribute INIT of instance um_O[15].u_ODDR_data in unit DDR_TX is not supported

Optimizing unit <DDR_TX_TEST> ...

Optimizing unit <DDR_TX> ...

Optimizing unit <DDR_TX_TOP> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block DDR_TX_TEST, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 147
 Flip-Flops                                            : 147

=========================================================================

=========================================================================
*                           Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : DDR_TX_TEST.ngr
Top Level Output File Name         : DDR_TX_TEST
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 142

Cell Usage :
# BELS                             : 407
#      GND                         : 1
#      INV                         : 9
#      LUT1                        : 128
#      LUT5                        : 1
#      LUT6                        : 2
#      MUXCY                       : 128
#      VCC                         : 1
#      XORCY                       : 137
# FlipFlops/Latches                : 215
#      FD                          : 18
#      FDC                         : 4
#      FDP                         : 124
#      FDR                         : 1
#      ODDR                        : 68
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 73
#      IBUF                        : 1
#      IBUFG                       : 1
#      OBUF                        : 3
#      OBUFDS_LVDSEXT_25           : 68
# Others                           : 1
#      PLL_ADV                     : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 5vfx130tff1738-1 


Slice Logic Utilization: 
 Number of Slice Registers:             215  out of  81920     0%  
 Number of Slice LUTs:                  140  out of  81920     0%  
    Number used as Logic:               140  out of  81920     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    221
   Number with an unused Flip Flop:       6  out of    221     2%  
   Number with an unused LUT:            81  out of    221    36%  
   Number of fully used LUT-FF pairs:   134  out of    221    60%  
   Number of unique control sets:         4

IO Utilization: 
 Number of IOs:                         142
 Number of bonded IOBs:                 142  out of    840    16%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     32     6%  
 Number of PLL_ADVs:                      1  out of      6    16%  

---------------------------