ddr_tx_test.twx

FPGA芯片与ADI公司的AD9779之间的通信

<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 10.1.02 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise
-intstyle ise -v 3 -s 1 -xml DDR_TX_TEST DDR_TX_TEST.ncd -o DDR_TX_TEST.twr
DDR_TX_TEST.pcf -ucf DDR_TX_UCF.ucf

</twCmdLine><twDesign>DDR_TX_TEST.ncd</twDesign><twPCF>DDR_TX_TEST.pcf</twPCF><twDevInfo arch="virtex5" pkg="ff1738"><twDevName>xc5vfx130t</twDevName><twSpeedGrade>-1</twSpeedGrade><twSpeedVer>ADVANCED 1.61 2008-05-28, STEPPING level 0</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo>INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst twConstType="PERIOD" ><twConstHead uID="0B0972B8"><twConstName UCFConstName="TIMESPEC &quot;TS_CLK_50M&quot; = PERIOD &quot;CLK_50M&quot; 20 ns HIGH 50 %;">TS_CLK_50M = PERIOD TIMEGRP &quot;CLK_50M&quot; 20 ns HIGH 50%;</twConstName><twItemCnt>45</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>26</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.564</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>18.436</twSlack><twSrc BELType="FF">u_DDR_TX_TOP/ClkCnt_0</twSrc><twDest BELType="FF">u_DDR_TX_TOP/ClkCnt_7</twDest><twTotPathDel>1.515</twTotPathDel><twClkSkew dest = "0.129" src = "0.143">0.014</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>u_DDR_TX_TOP/ClkCnt_0</twSrc><twDest BELType='FF'>u_DDR_TX_TOP/ClkCnt_7</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X50Y105.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_50M_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X50Y105.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;3&gt;</twComp><twBEL>u_DDR_TX_TOP/ClkCnt_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y105.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.377</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y105.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.499</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;3&gt;</twComp><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_lut&lt;0&gt;_INV_0</twBEL><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y106.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y106.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.168</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;7&gt;</twComp><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;7&gt;</twBEL><twBEL>u_DDR_TX_TOP/ClkCnt_7</twBEL></twPathDel><twLogDel>1.138</twLogDel><twRouteDel>0.377</twRouteDel><twTotDel>1.515</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_50M_BUFGP</twDestClk><twPctLog>75.1</twPctLog><twPctRoute>24.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>18.450</twSlack><twSrc BELType="FF">u_DDR_TX_TOP/ClkCnt_1</twSrc><twDest BELType="FF">u_DDR_TX_TOP/ClkCnt_7</twDest><twTotPathDel>1.501</twTotPathDel><twClkSkew dest = "0.129" src = "0.143">0.014</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>u_DDR_TX_TOP/ClkCnt_1</twSrc><twDest BELType='FF'>u_DDR_TX_TOP/ClkCnt_7</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X50Y105.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_50M_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X50Y105.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;3&gt;</twComp><twBEL>u_DDR_TX_TOP/ClkCnt_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y105.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.379</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y105.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;3&gt;</twComp><twBEL>u_DDR_TX_TOP/ClkCnt&lt;1&gt;_rt</twBEL><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y106.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y106.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.168</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;7&gt;</twComp><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;7&gt;</twBEL><twBEL>u_DDR_TX_TOP/ClkCnt_7</twBEL></twPathDel><twLogDel>1.122</twLogDel><twRouteDel>0.379</twRouteDel><twTotDel>1.501</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_50M_BUFGP</twDestClk><twPctLog>74.8</twPctLog><twPctRoute>25.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>18.457</twSlack><twSrc BELType="FF">u_DDR_TX_TOP/ClkCnt_0</twSrc><twDest BELType="FF">u_DDR_TX_TOP/ClkCnt_8</twDest><twTotPathDel>1.490</twTotPathDel><twClkSkew dest = "0.125" src = "0.143">0.018</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>u_DDR_TX_TOP/ClkCnt_0</twSrc><twDest BELType='FF'>u_DDR_TX_TOP/ClkCnt_8</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X50Y105.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_50M_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X50Y105.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;3&gt;</twComp><twBEL>u_DDR_TX_TOP/ClkCnt_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y105.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.377</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y105.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.499</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;3&gt;</twComp><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_lut&lt;0&gt;_INV_0</twBEL><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y106.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y106.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.104</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;7&gt;</twComp><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y107.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>u_DDR_TX_TOP/Mcount_ClkCnt_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y107.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.039</twDelInfo><twComp>u_DDR_TX_TOP/ClkCnt&lt;8&gt;</twComp><twBEL>u_DDR_TX_TOP/Mcount_ClkCnt_xor&lt;8&gt;</twBEL><twBEL>u_DDR_TX_TOP/ClkCnt_8</twBEL></twPathDel><twLogDel>1.113</twLogDel><twRouteDel>0.377</twRouteDel><twTotDel>1.490</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">CLK_50M_BUFGP</twDestClk><twPctLog>74.7</twPctLog><twPctRoute>25.3</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twConst twConstType="PERIOD" ><twConstHead uID="0B0971A0"><twConstName UCFConstName="TIMESPEC &quot;TS_USER_CLK&quot; = PERIOD &quot;USER_CLK&quot; 30 ns HIGH 50 %;">TS_USER_CLK = PERIOD TIMEGRP &quot;USER_CLK&quot; 30 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead></twConst><twConst twConstType="PERIOD" ><twConstHead uID="0B097088"><twConstName UCFConstName="TIMESPEC &quot;TS_USER_CLK&quot; = PERIOD &quot;USER_CLK&quot; 30 ns HIGH 50 %;">TS_u_PLL_tx_CLKOUT0_BUF = PERIOD TIMEGRP &quot;u_PLL_tx_CLKOUT0_BUF&quot; TS_USER_CLK /         4 HIGH 50%;</twConstName><twItemCnt>1216</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>544</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.046</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>1.727</twSlack><twSrc BELType="FF">DATA_TX_USER_1_31</twSrc><twDest BELType="FF">u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data</twDest><twTotPathDel>1.953</twTotPathDel><twClkSkew dest = "0.979" src = "0.988">0.009</twClkSkew><twDelConst>3.750</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.099" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.061</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>DATA_TX_USER_1_31</twSrc><twDest BELType='FF'>u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X1Y72.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">dbg_clk_122_OBUF</twSrcClk><twPathDel><twSite>SLICE_X1Y72.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>DATA_TX_USER_1&lt;31&gt;</twComp><twBEL>DATA_TX_USER_1_31</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X0Y159.D2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.069</twDelInfo><twComp>DATA_TX_USER_1&lt;31&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X0Y159.CLK</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.434</twDelInfo><twComp>u_DDR_TX_TOP/u_DDR_TX_1/data_tx_ds&lt;15&gt;</twComp><twBEL>u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data</twBEL></twPathDel><twLogDel>0.884</twLogDel><twRouteDel>1.069</twRouteDel><twTotDel>1.953</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="3.750">dbg_clk_122_OBUF</twDestClk><twPctLog>45.3</twPctLog><twPctRoute>54.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>1.893</twSlack><twSrc BELType="FF">DATA_TX_USER_3_28</twSrc><twDest BELType="FF">u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data</twDest><twTotPathDel>1.792</twTotPathDel><twClkSkew dest = "0.979" src = "0.983">0.004</twClkSkew><twDelConst>3.750</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.099" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.061</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>DATA_TX_USER_3_28</twSrc><twDest BELType='FF'>u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X0Y131.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">dbg_clk_122_OBUF</twSrcClk><twPathDel><twSite>SLICE_X0Y131.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>DATA_TX_USER_3&lt;31&gt;</twComp><twBEL>DATA_TX_USER_3_28</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X0Y279.D2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.887</twDelInfo><twComp>DATA_TX_USER_3&lt;28&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X0Y279.CLK</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.434</twDelInfo><twComp>u_DDR_TX_TOP/u_DDR_TX_3/data_tx_ds&lt;12&gt;</twComp><twBEL>u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data</twBEL></twPathDel><twLogDel>0.905</twLogDel><twRouteDel>0.887</twRouteDel><twTotDel>1.792</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="3.750">dbg_clk_122_OBUF</twDestClk><twPctLog>50.5</twPctLog><twPctRoute>49.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>1.894</twSlack><twSrc BELType="FF">DATA_TX_USER_3_29</twSrc><twDest BELType="FF">u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data</twDest><twTotPathDel>1.790</twTotPathDel><twClkSkew dest = "0.978" src = "0.983">0.005</twClkSkew><twDelConst>3.750</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.099" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.061</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>DATA_TX_USER_3_29</twSrc><twDest BELType='FF'>u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X0Y131.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">dbg_clk_122_OBUF</twSrcClk><twPathDel><twSite>SLICE_X0Y131.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>DATA_TX_USER_3&lt;31&gt;</twComp><twBEL>DATA_TX_USER_3_29</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X0Y277.D2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.885</twDelInfo><twComp>DATA_TX_USER_3&lt;29&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X0Y277.CLK</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.434</twDelInfo><twComp>u_DDR_TX_TOP/u_DDR_TX_3/data_tx_ds&lt;13&gt;</twComp><twBEL>u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data</twBEL></twPathDel><twLogDel>0.905</twLogDel><twRouteDel>0.885</twRouteDel><twTotDel>1.790</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="3.750">dbg_clk_122_OBUF</twDestClk><twPctLog>50.6</twPctLog><twPctRoute>49.4</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twConstRollupTable uID="0B0971A0"><twConstRollup name="TS_USER_CLK" fullName="TS_USER_CLK = PERIOD TIMEGRP &quot;USER_CLK&quot; 30 ns HIGH 50%;" type="origin" depth="0" requirement="30.000" prefType="period" actual="N/A" actualRollup="16.184" errors="0" errorRollup="0" items="0" itemsRollup="1216"/><twConstRollup name="TS_u_PLL_tx_CLKOUT0_BUF" fullName="TS_u_PLL_tx_CLKOUT0_BUF = PERIOD TIMEGRP &quot;u_PLL_tx_CLKOUT0_BUF&quot; TS_USER_CLK /         4 HIGH 50%;" type="child" depth="1" requirement="7.500" prefType="period" actual="4.046" actualRollup="N/A" errors="0" errorRollup="0" items="1216" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt>0</twUnmetConstCnt><twDataSheet twNameLen="15"><twClk2SUList twDestWidth = "7"><twDest>CLK_50M</twDest><twClk2SU><twSrc>CLK_50M</twSrc><twRiseRise>1.564</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList twDestWidth = "8"><twDest>USER_CLK</twDest><twClk2SU><twSrc>USER_CLK</twSrc><twRiseRise>1.911</twRiseRise><twRiseFall>2.023</twRiseFall></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum><twErrCnt>0</twErrCnt><twScore>0</twScore><twConstCov><twPathCnt>1261</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>393</twConnCnt></twConstCov><twStats><twMinPer>4.046</twMinPer><twFootnote number="1" /><twMaxFreq>247.158</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Tue Feb 17 17:44:42 2009 </twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 354 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>