cs.cdc

FPGA芯片与ADI公司的AD9779之间的通信

#ChipScope Core Inserter Project File Version 3.0
#Wed Dec 17 17:30:34 CST 2008
Project.device.designInputFile=E\:\\LVDS\\LVDS_DDR_List_FPGA2\\DDR_TX_TEST_cs.ngc
Project.device.designOutputFile=E\:\\LVDS\\LVDS_DDR_List_FPGA2\\DDR_TX_TEST_cs.ngc
Project.device.deviceFamily=14
Project.device.enableRPMs=true
Project.device.outputDirectory=E\:\\LVDS\\LVDS_DDR_List_FPGA2\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=1
Project.filter<0>=
Project.icon.boundaryScanChain=1
Project.icon.disableBUFGInsertion=false
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=CLK_50M_BUFGP
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=u_DDR_TX_0/data_tx_vld_ddr_r
Project.unit<0>.dataChannel<1>=u_DDR_TX_1/data_tx_vld_ddr_r
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=2
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=u_DDR_TX_0/data_tx_vld_ddr_r
Project.unit<0>.triggerChannel<0><1>=u_DDR_TX_1/data_tx_vld_ddr_r
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=0
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=2
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro