ddr_tx_test.restore

FPGA芯片与ADI公司的AD9779之间的通信

      "A" "" "" "" "PROP_CorgenRegenCore" "Under Current Project Setting" 
      "A" "" "" "" "PROP_CurrentFloorplanFile" "" 
      "A" "" "" "" "PROP_DefaultTBName" "Default" 
      "A" "" "" "" "PROP_DesignName" "DDR_TX_TEST" 
      "A" "" "" "" "PROP_Dummy" "dum1" 
      "A" "" "" "" "PROP_EnableWYSIWYG" "None" 
      "A" "" "" "" "PROP_Enable_Incremental_Messaging" "false" 
      "A" "" "" "" "PROP_Enable_Message_Capture" "true" 
      "A" "" "" "" "PROP_Enable_Message_Filtering" "false" 
      "A" "" "" "" "PROP_FitterReportFormat" "HTML" 
      "A" "" "" "" "PROP_FlowDebugLevel" "0" 
      "A" "" "" "" "PROP_FunctionBlockInputLimit" "38" 
      "A" "" "" "" "PROP_HierarchicalProjectType" "N/A" 
      "A" "" "" "" "PROP_ISimLibSearchOrderFile" "" 
      "A" "" "" "" "PROP_ISimOtherCompilerOptions_behav" "" 
      "A" "" "" "" "PROP_ISimOtherCompilerOptions_fit" "" 
      "A" "" "" "" "PROP_ISimOtherCompilerOptions_par" "" 
      "A" "" "" "" "PROP_ISimSDFTimingToBeRead" "Setup Time" 
      "A" "" "" "" "PROP_ISimSpecifyDefMacroAndValueChkSyntax" "" 
      "A" "" "" "" "PROP_ISimSpecifySearchDirectoryChkSyntax" "" 
      "A" "" "" "" "PROP_ISimUseCustomCompilationOrder" "false" 
      "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tb" "false" 
      "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tbw" "false" 
      "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_gen_tbw" "false" 
      "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_launch" "false" 
      "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tb" "false" 
      "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tbw" "false" 
      "A" "" "" "" "PROP_ISimUutInstName" "UUT" 
      "A" "" "" "" "PROP_ImpactProjectFile" "Default" 
      "A" "" "" "" "PROP_LastAppliedGoal" "Balanced" 
      "A" "" "" "" "PROP_LastAppliedStrategy" "Xilinx Default (unlocked)" 
      "A" "" "" "" "PROP_LastUnlockStatus" "false" 
      "A" "" "" "" "PROP_LoadPostTrceTSIFile" "false" 
      "A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time" 
      "A" "" "" "" "PROP_MapEffortLevel_virtex5" "High" 
      "A" "" "" "" "PROP_MapGlobalOptimization" "false" 
      "A" "" "" "" "PROP_MapLUTCombining_virtex5" "Off" 
      "A" "" "" "" "PROP_MapLogicOptimization_virtex5" "false" 
      "A" "" "" "" "PROP_MapPlacerCostTable_virtex5" "1" 
      "A" "" "" "" "PROP_MapPowerReduction_virtex5" "false" 
      "A" "" "" "" "PROP_MapRegDuplication_virtex5" "false" 
      "A" "" "" "" "PROP_ModelSimUseConfigName" "false" 
      "A" "" "" "" "PROP_OverwriteSym" "false" 
      "A" "" "" "" "PROP_Parse_Edif_Module" "false" 
      "A" "" "" "" "PROP_Parse_Target" "synthesis" 
      "A" "" "" "" "PROP_PartitionCreateDelete" "" 
      "A" "" "" "" "PROP_PartitionForcePlacement" "" 
      "A" "" "" "" "PROP_PartitionForceSynth" "" 
      "A" "" "" "" "PROP_PartitionForceTranslate" "" 
      "A" "" "" "" "PROP_PlsClockEnable" "true" 
      "A" "" "" "" "PROP_PostFitSimTop" "" 
      "A" "" "" "" "PROP_PostMapSimTop" "Module|TB_TX_RX" 
      "A" "" "" "" "PROP_PostParSimTop" "Module|TB_TX_RX" 
      "A" "" "" "" "PROP_PostSynthSimTop" "Module|TB_TX_RX" 
      "A" "" "" "" "PROP_PostTrceFastPath" "false" 
      "A" "" "" "" "PROP_PostTrceGenDatasheet" "true" 
      "A" "" "" "" "PROP_PostTrceGenTimegroups" "false" 
      "A" "" "" "" "PROP_PostXlateSimTop" "Module|TB_TX_RX" 
      "A" "" "" "" "PROP_PreTrceFastPath" "false" 
      "A" "" "" "" "PROP_PreTrceGenDatasheet" "true" 
      "A" "" "" "" "PROP_PreTrceGenTimegroups" "false" 
      "A" "" "" "" "PROP_PreTrceTSIFile" "" 
      "A" "" "" "" "PROP_PrecAddIOPads" "true" 
      "A" "" "" "" "PROP_PrecAdvFsmOptimization" "true" 
      "A" "" "" "" "PROP_PrecArrayBoundsCheck" "false" 
      "A" "" "" "" "PROP_PrecCreateUcfFromRtlConstraints" "false" 
      "A" "" "" "" "PROP_PrecEdif" "true" 
      "A" "" "" "" "PROP_PrecFsmEncoding" "Auto" 
      "A" "" "" "" "PROP_PrecFullCase" "false" 
      "A" "" "" "" "PROP_PrecInputSdcFile" "" 
      "A" "" "" "" "PROP_PrecOutputFileBase" "" 
      "A" "" "" "" "PROP_PrecParallelCase" "false" 
      "A" "" "" "" "PROP_PrecResourceSharing" "true" 
      "A" "" "" "" "PROP_PrecRptCriticalPaths" "true" 
      "A" "" "" "" "PROP_PrecRptMissingConstraints" "false" 
      "A" "" "" "" "PROP_PrecRptTimingSummary" "true" 
      "A" "" "" "" "PROP_PrecRptTimingViolations" "true" 
      "A" "" "" "" "PROP_PrecRptclockFreq" "true" 
      "A" "" "" "" "PROP_PrecRunRetiming" "false" 
      "A" "" "" "" "PROP_PrecShowClockDomainCrossing" "false" 
      "A" "" "" "" "PROP_PrecShowNetFanOut" "true" 
      "A" "" "" "" "PROP_PrecTranSetResetToLatches" "true" 
      "A" "" "" "" "PROP_PrecUseSafeFsm" "false" 
      "A" "" "" "" "PROP_PrecVerilog" "false" 
      "A" "" "" "" "PROP_PrecVhdl" "false" 
      "A" "" "" "" "PROP_PrecVhdlSyntax" "VHDL 93" 
      "A" "" "" "" "PROP_ProjectGeneratorType" "ProjNav" 
      "A" "" "" "" "PROP_ReduceControlSets_virtex5" "No" 
      "A" "" "" "" "PROP_SimDo" "true" 
      "A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false" 
      "A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false" 
      "A" "" "" "" "PROP_SimModelOtherNetgenOpts" "" 
      "A" "" "" "" "PROP_SimModelRetainHierarchy" "true" 
      "A" "" "" "" "PROP_SimUseCustom_behav" "false" 
      "A" "" "" "" "PROP_SimUseCustom_launchMSim" "false" 
      "A" "" "" "" "PROP_SimUseCustom_postMap" "false" 
      "A" "" "" "" "PROP_SimUseCustom_postPar" "false" 
      "A" "" "" "" "PROP_SimUseCustom_postXlate" "false" 
      "A" "" "" "" "PROP_SimUserCompileList_launchMSim" "" 
      "A" "" "" "" "PROP_StartImpView" "" 
      "A" "" "" "" "PROP_StopImpView" "AbstractSynthesis" 
      "A" "" "" "" "PROP_SynthCaseImplStyle" "None" 
      "A" "" "" "" "PROP_SynthDecoderExtract" "true" 
      "A" "" "" "" "PROP_SynthDisableIOInsertion" "false" 
      "A" "" "" "" "PROP_SynthEncoderExtract" "Yes" 
      "A" "" "" "" "PROP_SynthEnumEncoding" "default" 
      "A" "" "" "" "PROP_SynthExtractMux" "Yes" 
      "A" "" "" "" "PROP_SynthExtractRAM" "true" 
      "A" "" "" "" "PROP_SynthExtractROM" "true" 
      "A" "" "" "" "PROP_SynthFanout" "100" 
      "A" "" "" "" "PROP_SynthFsmEncode" "Auto" 
      "A" "" "" "" "PROP_SynthLogicalShifterExtract" "true" 
      "A" "" "" "" "PROP_SynthModular" "false" 
      "A" "" "" "" "PROP_SynthMultStyle" "LUT" 
      "A" "" "" "" "PROP_SynthNumCriticalPaths" "0" 
      "A" "" "" "" "PROP_SynthNumStartEndPoints" "0" 
      "A" "" "" "" "PROP_SynthOpt" "Speed" 
      "A" "" "" "" "PROP_SynthOptEffort" "Normal" 
      "A" "" "" "" "PROP_SynthPipelining" "true" 
      "A" "" "" "" "PROP_SynthProcBound" "true" 
      "A" "" "" "" "PROP_SynthResSharing" "true" 
      "A" "" "" "" "PROP_SynthResourceSharing" "true" 
      "A" "" "" "" "PROP_SynthRetiming" "false" 
      "A" "" "" "" "PROP_SynthShiftRegExtract" "true" 
      "A" "" "" "" "PROP_SynthSymbolicFsm" "true" 
      "A" "" "" "" "PROP_SynthTop" "Module|DDR_TX_TEST" 
      "A" "" "" "" "PROP_SynthUseFsmExplorerData" "false" 
      "A" "" "" "" "PROP_SynthXORCollapse" "true" 
      "A" "" "" "" "PROP_ToolPathChipscope" "" 
      "A" "" "" "" "PROP_ToolPathLeonardoSpectrum" "" 
      "A" "" "" "" "PROP_ToolPathModelSim" "" 
      "A" "" "" "" "PROP_ToolPathPrecision" "" 
      "A" "" "" "" "PROP_ToolPathSynplify" "" 
      "A" "" "" "" "PROP_ToolPathSynplifyPro" "" 
      "A" "" "" "" "PROP_Top_Level_Module_Type" "HDL" 
      "A" "" "" "" "PROP_UseDataGate" "true" 
      "A" "" "" "" "PROP_UseSmartGuide" "false" 
      "A" "" "" "" "PROP_UserBrowsedStrategyFiles" "" 
      "A" "" "" "" "PROP_UserConstraintEditorPreference" "Constraints Editor" 
      "A" "" "" "" "PROP_UserEditorCustomSetting" "" 
      "A" "" "" "" "PROP_UserEditorPreference" "ISE Text Editor" 
      "A" "" "" "" "PROP_Verilog2001" "true" 
      "A" "" "" "" "PROP_VirtexSynthAutoConstrain" "true" 
      "A" "" "" "" "PROP_WriteVHDLNetlist" "false" 
      "A" "" "" "" "PROP_WriteVendorConstFile" "true" 
      "A" "" "" "" "PROP_WriteVerilogNetlist" "false" 
      "A" "" "" "" "PROP_XPORTInpFileName" "" 
      "A" "" "" "" "PROP_XPORTInpFileType" "ABEL" 
      "A" "" "" "" "PROP_XPORTOutFileType" "VHDL" 
      "A" "" "" "" "PROP_XPORTlistInpFiles" "false" 
      "A" "" "" "" "PROP_XPowerOptInputTclScript" "" 
      "A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptOutputFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptVerboseRpt" "false" 
      "A" "" "" "" "PROP_XPowerOtherXPowerOpts" "" 
      "A" "" "" "" "PROP_XplorerMode" "Off" 
      "A" "" "" "" "PROP_bitgen_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_bitgen_otherCmdLineOptions_virtex5" "" 
      "A" "" "" "" "PROP_cpldBestFit" "false" 
      "A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source" 
      "A" "" "" "" "PROP_cpldfit_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_fitGenSimModel" "false" 
      "A" "" "" "" "PROP_hprep6_autosig" "false" 
      "A" "" "" "" "PROP_hprep6_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_ibiswriterGeneratePackageParasitics" "false" 
      "A" "" "" "" "PROP_ibiswriterShowAllModels" "false" 
      "A" "" "" "" "PROP_isimCompileForHdlDebug" "true" 
      "A" "" "" "" "PROP_isimIncreCompilation" "true" 
      "A" "" "" "" "PROP_isimSpecifyDefMacroAndValue" "" 
      "A" "" "" "" "PROP_isimSpecifySearchDirectory" "" 
      "A" "" "" "" "PROP_isimValueRangeCheck" "false" 
      "A" "" "" "" "PROP_lockPinsUcfFile" "" 
      "A" "" "" "" "PROP_mapIgnoreTimingConstraints" "false" 
      "A" "" "" "" "PROP_mapTimingAnalyzerLoadDesign" "true" 
      "A" "" "" "" "PROP_mapUseRLOCConstraints" "true" 
      "A" "" "" "" "PROP_map_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_mpprRsltToCopy" "" 
      "A" "" "" "" "PROP_mpprViewPadRptsForAllRslt" "true" 
      "A" "" "" "" "PROP_mpprViewParRptsForAllRslt" "true" 
      "A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true" 
      "A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_parIgnoreTimingConstraints" "false" 
      "A" "" "" "" "PROP_parTimingAnalyzerLoadDesign" "true" 
      "A" "" "" "" "PROP_parUseTimingConstraints" "true" 
      "A" "" "" "" "PROP_par_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_primeCorrelateOutput" "false" 
      "A" "" "" "" "PROP_primeFlatternOutputNetlist" "false" 
      "A" "" "" "" "PROP_primeTopLevelModule" "" 
      "A" "" "" "" "PROP_primetimeBlockRamData" "" 
      "A" "" "" "" "PROP_taengine_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_usedsp48_virtex5" "Auto" 
      "A" "" "" "" "PROP_xcpldFitDesInit" "Low" 
      "A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32" 
      "A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true" 
      "A" "" "" "" "PROP_xcpldFitDesSlew" "Fast" 
      "A" "" "" "" "PROP_xcpldFitDesTimingCst" "true" 
      "A" "" "" "" "PROP_xcpldFitDesTriMode" "Keeper" 
      "A" "" "" "" "PROP_xcpldFitDesUnused" "Keeper" 
      "A" "" "" "" "PROP_xcpldFitDesVolt" "LVCMOS18" 
      "A" "" "" "" "PROP_xcpldFitTemplate_xpla3" "Optimize Density" 
      "A" "" "" "" "PROP_xcpldFittimRptOption" "Summary" 
      "A" "" "" "" "PROP_xcpldUseGlobalClocks" "true" 
      "A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true" 
      "A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true" 
      "A" "" "" "" "PROP_xcpldUseLocConst" "Always" 
      "A" "" "" "" "PROP_xilxBitgCfg_BPI_Page_Size_virtex5" "1" 
      "A" "" "" "" "PROP_xilxBitgCfg_Busy_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Clk" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Clk_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Code" "0xFFFFFFFF" 
      "A" "" "" "" "PROP_xilxBitgCfg_Code_virtex5" "0xFFFFFFFF" 
      "A" "" "" "" "PROP_xilxBitgCfg_Cs_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_DCIUpdateMode_virtex5" "As Required" 
      "A" "" "" "" "PROP_xilxBitgCfg_Din_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Done_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel0" "11111" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel1" "11111" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel2" "11111" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel3" "11111" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_Init_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M0" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M0_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M1" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M1_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M2" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M2_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Pgm_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_PwrDown_Safe_Temp_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_Rate" "4" 
      "A" "" "" "" "PROP_xilxBitgCfg_Rate_virtex5" "2" 
      "A" "" "" "" "PROP_xilxBitgCfg_Rdwr_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Retain_Config_Status_Register_Values_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_SelectMAP_Abort_Sequence_virtex5" "Enable" 
      "A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TCK_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TDI_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TDO" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TDO_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TMS" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TMS_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Unused" "Pull Down" 
      "A" "" "" "" "PROP_xilxBitgCfg_Unused_virtex5" "Pull Down" 
      "A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration" 
      "A" "" "" "" "PROP_xilxBitgReadBk_Sec_virtex5" "Enable Readback and Reconfiguration" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "Default (4)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_Done_virtex5" "Default (4)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut_virtex5" "Default (5)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle_virtex5" "Auto" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL_virtex5" "Default (NoWait)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelSet" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn_virtex5" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_virtex5" "CCLK" 
      "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_IntDone_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false" 
      "A" "" "" "" "PROP_xilxMapCoverMode" "Area" 
      "A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false" 
      "A" "" "" "" "PROP_xilxMapMaxCompression_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapReplicateLogic" "true" 
      "A" "" "" "" "PROP_xilxMapReportDetail" "false" 
      "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false" 
      "A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false" 
      "A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true" 
      "A" "" "" "" "PROP_xilxNgdbldIOPads" "false" 
      "A" "" "" "" "PROP_xilxNgdbldMacro" "" 
      "A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp" 
      "A" "" "" "" "PROP_xilxNgdbldUR" ""