ddr_tx.v

FPGA芯片与ADI公司的AD9779之间的通信

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:57:47 12/09/2008 
// Design Name: 
// Module Name:    DDR_TX 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DDR_TX(
		output[15:0] DATA_TX_P,
      output[15:0] DATA_TX_N,
		
      output CLOCK_TX_P,
      output CLOCK_TX_N,
  
      input[31:0] DATA_TX_USER,

		input USER_CLK,
		
		input RESET
	   );
	 
	wire[15:0] data_tx_ds;
	wire[31:0] data_tx_ddr;
	wire      clk_tx_ds;

	genvar i;
   generate
       for (i=0; i < 16; i=i+1) 
       begin: um_O
           ODDR #(
			        .DDR_CLK_EDGE("OPPOSITE_EDGE"),
					  .INIT(0),
					  .SRTYPE("ASYNC")
					  )
			  u_ODDR_data(
			        .D1(DATA_TX_USER[i]),
					  .D2(DATA_TX_USER[i+16]),
					  .C(USER_CLK),
					  .CE(1),
					  .Q(data_tx_ds[i]),
					  .R(RESET),
					  .S(0)
					  );
			  
			  OBUFDS_LVDSEXT_25  
			  u_OBUFDS_data(
						 .I(data_tx_ds[i]),
						 .O(DATA_TX_P[i]),
                   .OB(DATA_TX_N[i])
						 ); 
       end
   endgenerate	
	
	ODDR #(
		  .DDR_CLK_EDGE("OPPOSITE_EDGE"),
	     .INIT(0),
		  .SRTYPE("ASYNC")
		  )
	u_ODDR_clk(
		  .D1(1),
		  .D2(0),
		  .C(USER_CLK),
		  .CE(1),
		  .Q(clk_tx_ds),
		  .R(RESET),
		  .S(0)
		  );
	  
	OBUFDS_LVDSEXT_25  
	u_OBUFDS_clk(
	   	 .I(clk_tx_ds),
			 .O(CLOCK_TX_P),
			 .OB(CLOCK_TX_N)
			 ); 
			 	
endmodule