ddr_tx_test.twr

FPGA芯片与ADI公司的AD9779之间的通信

 1216 paths analyzed, 544 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   4.046ns.
--------------------------------------------------------------------------------
Slack:                  1.727ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DATA_TX_USER_1_31 (FF)
  Destination:          u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data (FF)
  Requirement:          3.750ns
  Data Path Delay:      1.953ns (Levels of Logic = 0)
  Clock Path Skew:      -0.009ns (0.979 - 0.988)
  Source Clock:         dbg_clk_122_OBUF rising at 0.000ns
  Destination Clock:    dbg_clk_122_OBUF falling at 3.750ns
  Clock Uncertainty:    0.061ns

  Clock Uncertainty:          0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.099ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: DATA_TX_USER_1_31 to u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y72.DQ       Tcko                  0.450   DATA_TX_USER_1<31>
                                                       DATA_TX_USER_1_31
    OLOGIC_X0Y159.D2     net (fanout=2)        1.069   DATA_TX_USER_1<31>
    OLOGIC_X0Y159.CLK    Todck                 0.434   u_DDR_TX_TOP/u_DDR_TX_1/data_tx_ds<15>
                                                       u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data
    -------------------------------------------------  ---------------------------
    Total                                      1.953ns (0.884ns logic, 1.069ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack:                  1.893ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DATA_TX_USER_3_28 (FF)
  Destination:          u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data (FF)
  Requirement:          3.750ns
  Data Path Delay:      1.792ns (Levels of Logic = 0)
  Clock Path Skew:      -0.004ns (0.979 - 0.983)
  Source Clock:         dbg_clk_122_OBUF rising at 0.000ns
  Destination Clock:    dbg_clk_122_OBUF falling at 3.750ns
  Clock Uncertainty:    0.061ns

  Clock Uncertainty:          0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.099ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: DATA_TX_USER_3_28 to u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y131.AQ      Tcko                  0.471   DATA_TX_USER_3<31>
                                                       DATA_TX_USER_3_28
    OLOGIC_X0Y279.D2     net (fanout=2)        0.887   DATA_TX_USER_3<28>
    OLOGIC_X0Y279.CLK    Todck                 0.434   u_DDR_TX_TOP/u_DDR_TX_3/data_tx_ds<12>
                                                       u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data
    -------------------------------------------------  ---------------------------
    Total                                      1.792ns (0.905ns logic, 0.887ns route)
                                                       (50.5% logic, 49.5% route)

--------------------------------------------------------------------------------
Slack:                  1.894ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DATA_TX_USER_3_29 (FF)
  Destination:          u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data (FF)
  Requirement:          3.750ns
  Data Path Delay:      1.790ns (Levels of Logic = 0)
  Clock Path Skew:      -0.005ns (0.978 - 0.983)
  Source Clock:         dbg_clk_122_OBUF rising at 0.000ns
  Destination Clock:    dbg_clk_122_OBUF falling at 3.750ns
  Clock Uncertainty:    0.061ns

  Clock Uncertainty:          0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.099ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: DATA_TX_USER_3_29 to u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y131.BQ      Tcko                  0.471   DATA_TX_USER_3<31>
                                                       DATA_TX_USER_3_29
    OLOGIC_X0Y277.D2     net (fanout=2)        0.885   DATA_TX_USER_3<29>
    OLOGIC_X0Y277.CLK    Todck                 0.434   u_DDR_TX_TOP/u_DDR_TX_3/data_tx_ds<13>
                                                       u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data
    -------------------------------------------------  ---------------------------
    Total                                      1.790ns (0.905ns logic, 0.885ns route)
                                                       (50.6% logic, 49.4% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_USER_CLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_USER_CLK                    |     30.000ns|          N/A|     16.184ns|            0|            0|            0|         1216|
| TS_u_PLL_tx_CLKOUT0_BUF       |      7.500ns|      4.046ns|          N/A|            0|            0|         1216|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK_50M
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_50M        |    1.564|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock USER_CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
USER_CLK       |    1.911|         |    2.023|         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 1261 paths, 0 nets, and 393 connections

Design statistics:
   Minimum period:   4.046ns{1}   (Maximum frequency: 247.158MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Tue Feb 17 17:44:42 2009 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 354 MB