ddr_tx_test.twr

FPGA芯片与ADI公司的AD9779之间的通信

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Release 10.1.02 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise
-intstyle ise -v 3 -s 1 -xml DDR_TX_TEST DDR_TX_TEST.ncd -o DDR_TX_TEST.twr
DDR_TX_TEST.pcf -ucf DDR_TX_UCF.ucf

Design file:              DDR_TX_TEST.ncd
Physical constraint file: DDR_TX_TEST.pcf
Device,package,speed:     xc5vfx130t,ff1738,-1 (ADVANCED 1.61 2008-05-28, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_CLK_50M = PERIOD TIMEGRP "CLK_50M" 20 ns HIGH 50%;

 45 paths analyzed, 26 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   1.564ns.
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Slack:                  18.436ns (requirement - (data path - clock path skew + uncertainty))
  Source:               u_DDR_TX_TOP/ClkCnt_0 (FF)
  Destination:          u_DDR_TX_TOP/ClkCnt_7 (FF)
  Requirement:          20.000ns
  Data Path Delay:      1.515ns (Levels of Logic = 2)
  Clock Path Skew:      -0.014ns (0.129 - 0.143)
  Source Clock:         CLK_50M_BUFGP rising at 0.000ns
  Destination Clock:    CLK_50M_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: u_DDR_TX_TOP/ClkCnt_0 to u_DDR_TX_TOP/ClkCnt_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y105.AQ     Tcko                  0.471   u_DDR_TX_TOP/ClkCnt<3>
                                                       u_DDR_TX_TOP/ClkCnt_0
    SLICE_X50Y105.A4     net (fanout=1)        0.377   u_DDR_TX_TOP/ClkCnt<0>
    SLICE_X50Y105.COUT   Topcya                0.499   u_DDR_TX_TOP/ClkCnt<3>
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_lut<0>_INV_0
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>
    SLICE_X50Y106.CIN    net (fanout=1)        0.000   u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>
    SLICE_X50Y106.CLK    Tcinck                0.168   u_DDR_TX_TOP/ClkCnt<7>
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_cy<7>
                                                       u_DDR_TX_TOP/ClkCnt_7
    -------------------------------------------------  ---------------------------
    Total                                      1.515ns (1.138ns logic, 0.377ns route)
                                                       (75.1% logic, 24.9% route)

--------------------------------------------------------------------------------
Slack:                  18.450ns (requirement - (data path - clock path skew + uncertainty))
  Source:               u_DDR_TX_TOP/ClkCnt_1 (FF)
  Destination:          u_DDR_TX_TOP/ClkCnt_7 (FF)
  Requirement:          20.000ns
  Data Path Delay:      1.501ns (Levels of Logic = 2)
  Clock Path Skew:      -0.014ns (0.129 - 0.143)
  Source Clock:         CLK_50M_BUFGP rising at 0.000ns
  Destination Clock:    CLK_50M_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: u_DDR_TX_TOP/ClkCnt_1 to u_DDR_TX_TOP/ClkCnt_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y105.BQ     Tcko                  0.471   u_DDR_TX_TOP/ClkCnt<3>
                                                       u_DDR_TX_TOP/ClkCnt_1
    SLICE_X50Y105.B4     net (fanout=1)        0.379   u_DDR_TX_TOP/ClkCnt<1>
    SLICE_X50Y105.COUT   Topcyb                0.483   u_DDR_TX_TOP/ClkCnt<3>
                                                       u_DDR_TX_TOP/ClkCnt<1>_rt
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>
    SLICE_X50Y106.CIN    net (fanout=1)        0.000   u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>
    SLICE_X50Y106.CLK    Tcinck                0.168   u_DDR_TX_TOP/ClkCnt<7>
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_cy<7>
                                                       u_DDR_TX_TOP/ClkCnt_7
    -------------------------------------------------  ---------------------------
    Total                                      1.501ns (1.122ns logic, 0.379ns route)
                                                       (74.8% logic, 25.2% route)

--------------------------------------------------------------------------------
Slack:                  18.457ns (requirement - (data path - clock path skew + uncertainty))
  Source:               u_DDR_TX_TOP/ClkCnt_0 (FF)
  Destination:          u_DDR_TX_TOP/ClkCnt_8 (FF)
  Requirement:          20.000ns
  Data Path Delay:      1.490ns (Levels of Logic = 3)
  Clock Path Skew:      -0.018ns (0.125 - 0.143)
  Source Clock:         CLK_50M_BUFGP rising at 0.000ns
  Destination Clock:    CLK_50M_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: u_DDR_TX_TOP/ClkCnt_0 to u_DDR_TX_TOP/ClkCnt_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y105.AQ     Tcko                  0.471   u_DDR_TX_TOP/ClkCnt<3>
                                                       u_DDR_TX_TOP/ClkCnt_0
    SLICE_X50Y105.A4     net (fanout=1)        0.377   u_DDR_TX_TOP/ClkCnt<0>
    SLICE_X50Y105.COUT   Topcya                0.499   u_DDR_TX_TOP/ClkCnt<3>
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_lut<0>_INV_0
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>
    SLICE_X50Y106.CIN    net (fanout=1)        0.000   u_DDR_TX_TOP/Mcount_ClkCnt_cy<3>
    SLICE_X50Y106.COUT   Tbyp                  0.104   u_DDR_TX_TOP/ClkCnt<7>
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_cy<7>
    SLICE_X50Y107.CIN    net (fanout=1)        0.000   u_DDR_TX_TOP/Mcount_ClkCnt_cy<7>
    SLICE_X50Y107.CLK    Tcinck                0.039   u_DDR_TX_TOP/ClkCnt<8>
                                                       u_DDR_TX_TOP/Mcount_ClkCnt_xor<8>
                                                       u_DDR_TX_TOP/ClkCnt_8
    -------------------------------------------------  ---------------------------
    Total                                      1.490ns (1.113ns logic, 0.377ns route)
                                                       (74.7% logic, 25.3% route)

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================================================================================
Timing constraint: TS_USER_CLK = PERIOD TIMEGRP "USER_CLK" 30 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
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================================================================================
Timing constraint: TS_u_PLL_tx_CLKOUT0_BUF = PERIOD TIMEGRP 
"u_PLL_tx_CLKOUT0_BUF" TS_USER_CLK /         4 HIGH 50%;