📄 ddr_tx_test.par
字号:
Release 10.1.02 par K.37 (nt)Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.GYB:: Tue Feb 17 17:38:33 2009par -w -intstyle ise -ol std -t 1 DDR_TX_TEST_map.ncd DDR_TX_TEST.ncd
DDR_TX_TEST.pcf Constraints file: DDR_TX_TEST.pcf.Loading device for application Rf_Device from file '5vfx130t.nph' in environment E:\FPGA\Xilinx\10.1\ISE. "DDR_TX_TEST" is an NCD, version 3.2, device xc5vfx130t, package ff1738, speed -1Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)Device speed data version: "ADVANCED 1.61 2008-05-28".Device Utilization Summary: Number of BUFGs 2 out of 32 6% Number of External IOBs 6 out of 840 1% Number of LOCed IOBs 5 out of 6 83% Number of External IOBMs 68 out of 420 16% Number of LOCed IOBMs 68 out of 68 100% Number of External IOBSs 68 out of 420 16% Number of LOCed IOBSs 68 out of 68 100% Number of OLOGICs 68 out of 1040 6% Number of PLL_ADVs 1 out of 6 16% Number of Slice Registers 147 out of 81920 1% Number used as Flip Flops 147 Number used as Latches 0 Number used as LatchThrus 0 Number of Slice LUTS 140 out of 81920 1% Number of Slice LUT-Flip Flop pairs 150 out of 81920 1%Overall effort level (-ol): Standard Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 1 mins Finished initial Timing Analysis. REAL time: 1 mins Starting RouterPhase 1: 832 unrouted; REAL time: 1 mins 12 secs Phase 2: 495 unrouted; REAL time: 1 mins 14 secs Phase 3: 16 unrouted; REAL time: 1 mins 15 secs Phase 4: 16 unrouted; (0) REAL time: 1 mins 57 secs Phase 5: 16 unrouted; (0) REAL time: 1 mins 57 secs Phase 6: 16 unrouted; (0) REAL time: 1 mins 57 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 59 secs Updating file: DDR_TX_TEST.ncd with current fully routed design.Phase 8: 0 unrouted; (0) REAL time: 2 mins 1 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 1 secs Phase 10: 0 unrouted; (0) REAL time: 2 mins 3 secs Total REAL time to Router completion: 2 mins 4 secs Total CPU time to Router completion: 1 mins 17 secs Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+| dbg_clk_122_OBUF |BUFGCTRL_X0Y27| No | 101 | 0.196 | 2.304 |+---------------------+--------------+------+------+------------+-------------+| CLK_50M_BUFGP |BUFGCTRL_X0Y22| No | 3 | 0.008 | 1.790 |+---------------------+--------------+------+------+------------+-------------+|u_DDR_TX_TOP/ClkCnt< | | | | | || 8> | Local| | 5 | 0.329 | 1.326 |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.Timing Score: 0INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.Number of Timing Constraints that were not applied: 1Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ TS_u_PLL_tx_CLKOUT0_BUF = PERIOD TIMEGRP | SETUP | 1.727ns| 4.046ns| 0| 0 "u_PLL_tx_CLKOUT0_BUF" TS_USER_CLK / | HOLD | 0.673ns| | 0| 0 4 HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------ TS_CLK_50M = PERIOD TIMEGRP "CLK_50M" 20 | SETUP | 18.436ns| 1.564ns| 0| 0 ns HIGH 50% | HOLD | 0.683ns| | 0| 0------------------------------------------------------------------------------------------------------ TS_USER_CLK = PERIOD TIMEGRP "USER_CLK" 3 | N/A | N/A| N/A| N/A| N/A 0 ns HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------Derived Constraint ReportDerived Constraints for TS_USER_CLK+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+| | Period | Actual Period | Timing Errors | Paths Analyzed || Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+|TS_USER_CLK | 30.000ns| N/A| 16.184ns| 0| 0| 0| 1216|| TS_u_PLL_tx_CLKOUT0_BUF | 7.500ns| 4.046ns| N/A| 0| 0| 1216| 0|+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 4 mins 53 secs Total CPU time to PAR completion: 2 mins 52 secs Peak Memory Usage: 381 MBPlacer: Placement generated during map.Routing: Completed - No errors found.Timing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file DDR_TX_TEST.ncdPAR done!⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -