ddr_tx_test.pcf

FPGA芯片与ADI公司的AD9779之间的通信

COMP "DATA_TX_P_3<6>" LOCATE = SITE "T37" LEVEL 1;
COMP "DATA_TX_P_3<14>" LOCATE = SITE "F39" LEVEL 1;
COMP "DATA_TX_P_3<7>" LOCATE = SITE "R39" LEVEL 1;
COMP "DATA_TX_P_3<15>" LOCATE = SITE "E39" LEVEL 1;
COMP "DATA_TX_P_3<8>" LOCATE = SITE "R37" LEVEL 1;
COMP "DATA_TX_P_3<9>" LOCATE = SITE "P38" LEVEL 1;
COMP "CLK_50M" LOCATE = SITE "K29" LEVEL 1;
TIMEGRP u_PLL_tx_CLKOUT0_BUF = BEL "DATA_TX_USER_0_30" BEL "DATA_TX_USER_0_29"
        BEL "DATA_TX_USER_0_28" BEL "DATA_TX_USER_0_27" BEL
        "DATA_TX_USER_0_26" BEL "DATA_TX_USER_0_25" BEL "DATA_TX_USER_0_22"
        BEL "DATA_TX_USER_0_24" BEL "DATA_TX_USER_0_23" BEL
        "DATA_TX_USER_0_21" BEL "DATA_TX_USER_0_20" BEL "DATA_TX_USER_0_19"
        BEL "DATA_TX_USER_0_18" BEL "DATA_TX_USER_0_17" BEL
        "DATA_TX_USER_0_16" BEL "DATA_TX_USER_0_13" BEL "DATA_TX_USER_0_14"
        BEL "DATA_TX_USER_0_12" BEL "DATA_TX_USER_0_11" BEL
        "DATA_TX_USER_0_10" BEL "DATA_TX_USER_0_9" BEL "DATA_TX_USER_0_8" BEL
        "DATA_TX_USER_0_7" BEL "DATA_TX_USER_0_6" BEL "DATA_TX_USER_0_5" BEL
        "DATA_TX_USER_0_4" BEL "DATA_TX_USER_0_3" BEL "DATA_TX_USER_0_2" BEL
        "DATA_TX_USER_0_1" BEL "DATA_TX_USER_0_0" BEL "DATA_TX_USER_1_28" BEL
        "DATA_TX_USER_1_30" BEL "DATA_TX_USER_1_29" BEL "DATA_TX_USER_1_27"
        BEL "DATA_TX_USER_1_26" BEL "DATA_TX_USER_1_25" BEL
        "DATA_TX_USER_1_24" BEL "DATA_TX_USER_1_23" BEL "DATA_TX_USER_1_22"
        BEL "DATA_TX_USER_1_21" BEL "DATA_TX_USER_1_20" BEL
        "DATA_TX_USER_1_19" BEL "DATA_TX_USER_1_18" BEL "DATA_TX_USER_1_17"
        BEL "DATA_TX_USER_1_16" BEL "DATA_TX_USER_1_14" BEL
        "DATA_TX_USER_1_11" BEL "DATA_TX_USER_1_13" BEL "DATA_TX_USER_1_12"
        BEL "DATA_TX_USER_1_10" BEL "DATA_TX_USER_1_9" BEL "DATA_TX_USER_1_8"
        BEL "DATA_TX_USER_1_7" BEL "DATA_TX_USER_1_6" BEL "DATA_TX_USER_1_5"
        BEL "DATA_TX_USER_1_4" BEL "DATA_TX_USER_1_3" BEL "DATA_TX_USER_1_2"
        BEL "DATA_TX_USER_1_1" BEL "DATA_TX_USER_1_0" BEL "DATA_TX_USER_2_30"
        BEL "DATA_TX_USER_2_29" BEL "DATA_TX_USER_2_26" BEL
        "DATA_TX_USER_2_28" BEL "DATA_TX_USER_2_27" BEL "DATA_TX_USER_2_25"
        BEL "DATA_TX_USER_2_24" BEL "DATA_TX_USER_2_23" BEL
        "DATA_TX_USER_2_22" BEL "DATA_TX_USER_2_21" BEL "DATA_TX_USER_2_20"
        BEL "DATA_TX_USER_2_17" BEL "DATA_TX_USER_2_19" BEL
        "DATA_TX_USER_2_18" BEL "DATA_TX_USER_2_16" BEL "DATA_TX_USER_2_14"
        BEL "DATA_TX_USER_2_13" BEL "DATA_TX_USER_2_12" BEL
        "DATA_TX_USER_2_11" BEL "DATA_TX_USER_2_8" BEL "DATA_TX_USER_2_10" BEL
        "DATA_TX_USER_2_9" BEL "DATA_TX_USER_2_7" BEL "DATA_TX_USER_2_6" BEL
        "DATA_TX_USER_2_5" BEL "DATA_TX_USER_2_4" BEL "DATA_TX_USER_2_3" BEL
        "DATA_TX_USER_2_2" BEL "DATA_TX_USER_2_1" BEL "DATA_TX_USER_2_0" BEL
        "DATA_TX_USER_3_30" BEL "DATA_TX_USER_3_29" BEL "DATA_TX_USER_3_28"
        BEL "DATA_TX_USER_3_27" BEL "DATA_TX_USER_3_26" BEL
        "DATA_TX_USER_3_23" BEL "DATA_TX_USER_3_25" BEL "DATA_TX_USER_3_24"
        BEL "DATA_TX_USER_3_22" BEL "DATA_TX_USER_3_21" BEL
        "DATA_TX_USER_3_20" BEL "DATA_TX_USER_3_19" BEL "DATA_TX_USER_3_18"
        BEL "DATA_TX_USER_3_17" BEL "DATA_TX_USER_3_16" BEL
        "DATA_TX_USER_3_14" BEL "DATA_TX_USER_3_13" BEL "DATA_TX_USER_3_12"
        BEL "DATA_TX_USER_3_11" BEL "DATA_TX_USER_3_10" BEL "DATA_TX_USER_3_9"
        BEL "DATA_TX_USER_3_6" BEL "DATA_TX_USER_3_8" BEL "DATA_TX_USER_3_7"
        BEL "DATA_TX_USER_3_5" BEL "DATA_TX_USER_3_4" BEL "DATA_TX_USER_3_3"
        BEL "DATA_TX_USER_3_2" BEL "DATA_TX_USER_3_1" BEL "DATA_TX_USER_3_0"
        BEL "DATA_TX_USER_0_31" BEL "DATA_TX_USER_0_15" BEL
        "DATA_TX_USER_1_31" BEL "DATA_TX_USER_1_15" BEL "DATA_TX_USER_2_31"
        BEL "DATA_TX_USER_2_15" BEL "DATA_TX_USER_3_31" BEL
        "DATA_TX_USER_3_15" BEL "u_DDR_TX_TOP/u_DDR_TX_0/u_ODDR_clk" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[0].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[1].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[2].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[3].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[4].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[5].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[6].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[7].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[8].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[9].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[10].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[11].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[12].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[13].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[14].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_0/um_O[15].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/u_ODDR_clk" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[0].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[1].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[2].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[3].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[4].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[5].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[6].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[7].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[8].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[9].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[10].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[11].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[12].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[13].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[14].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/u_ODDR_clk" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[0].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[1].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[2].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[3].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[4].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[5].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[6].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[7].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[8].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[9].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[10].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[11].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[12].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[13].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[14].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_2/um_O[15].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/u_ODDR_clk" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[0].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[1].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[2].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[3].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[4].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[5].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[6].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[7].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[8].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[9].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[10].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[11].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[14].u_ODDR_data" BEL
        "u_DDR_TX_TOP/u_DDR_TX_3/um_O[15].u_ODDR_data" BEL "dbg_clk_122";
TIMEGRP CLK_50M = BEL "u_DDR_TX_TOP/ClkCnt_8" BEL "u_DDR_TX_TOP/ClkCnt_7" BEL
        "u_DDR_TX_TOP/ClkCnt_6" BEL "u_DDR_TX_TOP/ClkCnt_5" BEL
        "u_DDR_TX_TOP/ClkCnt_4" BEL "u_DDR_TX_TOP/ClkCnt_3" BEL
        "u_DDR_TX_TOP/ClkCnt_2" BEL "u_DDR_TX_TOP/ClkCnt_1" BEL
        "u_DDR_TX_TOP/ClkCnt_0";
PIN u_PLL_tx/PLL_ADV_INST_pins<4> = BEL "u_PLL_tx/PLL_ADV_INST" PINNAME
        CLKIN1;
TIMEGRP USER_CLK = BEL "dbg_clk_30" PIN "u_PLL_tx/PLL_ADV_INST_pins<4>";
TS_CLK_50M = PERIOD TIMEGRP "CLK_50M" 20 ns HIGH 50%;
TS_USER_CLK = PERIOD TIMEGRP "USER_CLK" 30 ns HIGH 50%;
TS_u_PLL_tx_CLKOUT0_BUF = PERIOD TIMEGRP "u_PLL_tx_CLKOUT0_BUF" TS_USER_CLK /
        4 HIGH 50%;
SCHEMATIC END;