radix4_256fft.map.rpt

基于VHDL语言的一个FFT快速傅里叶变换程序采用4蝶形算法

; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Feb 22 17:48:00 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off radix4_256fft -c radix4_256fft
Info: Found 1 design units, including 1 entities, in source file fft_data_buf.v
    Info: Found entity 1: fft_data_buf
Info: Found 1 design units, including 1 entities, in source file rofactor/rofactor.v
    Info: Found entity 1: rofactor
Info: Found 1 design units, including 1 entities, in source file mulfactor/factor_rom_I.v
    Info: Found entity 1: factor_rom_I
Info: Found 1 design units, including 1 entities, in source file mulfactor/factor_rom_Q.v
    Info: Found entity 1: factor_rom_Q
Info: Found 1 design units, including 1 entities, in source file mulfactor/fmta.v
    Info: Found entity 1: fmta
Info: Found 1 design units, including 1 entities, in source file mulfactor/fmts.v
    Info: Found entity 1: fmts
Info: Found 1 design units, including 1 entities, in source file mulfactor/mulfactor.v
    Info: Found entity 1: mulfactor
Info: Found 1 design units, including 1 entities, in source file div4limit/div4limit.v
    Info: Found entity 1: div4limit
Info: Found 1 design units, including 1 entities, in source file cfft4/cfft4.v
    Info: Found entity 1: cfft4
Info: Found 1 design units, including 1 entities, in source file addr_gen/addr_gen.v
    Info: Found entity 1: addr_gen
Info: Found 1 design units, including 1 entities, in source file radix4_256fft_test.bdf
    Info: Found entity 1: radix4_256fft_test
Info: Found 1 design units, including 1 entities, in source file radix4_256fft.bdf
    Info: Found entity 1: radix4_256fft
Info: Elaborating entity "radix4_256fft" for the top level hierarchy
Info: Elaborating entity "addr_gen" for hierarchy "addr_gen:inst1"
Info: Elaborating entity "div4limit" for hierarchy "div4limit:inst13"
Info: Elaborating entity "mulfactor" for hierarchy "mulfactor:inst3"
Info: Elaborating entity "factor_rom_I" for hierarchy "mulfactor:inst3|factor_rom_I:wprom_I"
Info: Elaborating entity "factor_rom_Q" for hierarchy "mulfactor:inst3|factor_rom_Q:wprom_Q"
Info: Elaborating entity "fmts" for hierarchy "mulfactor:inst3|fmts:mul_s"
Info: Found 1 design units, including 1 entities, in source file ../quartus/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Elaborating entity "altmult_add" for hierarchy "mulfactor:inst3|fmts:mul_s|altmult_add:ALTMULT_ADD_component"
Info: Elaborated megafunction instantiation "mulfactor:inst3|fmts:mul_s|altmult_add:ALTMULT_ADD_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_clp2.tdf
    Info: Found entity 1: mult_add_clp2
Info: Elaborating entity "mult_add_clp2" for hierarchy "mulfactor:inst3|fmts:mul_s|altmult_add:ALTMULT_ADD_component|mult_add_clp2:auto_generated"
Info: Elaborating entity "fmta" for hierarchy "mulfactor:inst3|fmta:mul_a"
Info: Elaborating entity "altmult_add" for hierarchy "mulfactor:inst3|fmta:mul_a|altmult_add:ALTMULT_ADD_component"
Info: Elaborated megafunction instantiation "mulfactor:inst3|fmta:mul_a|altmult_add:ALTMULT_ADD_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_bkp2.tdf
    Info: Found entity 1: mult_add_bkp2
Info: Elaborating entity "mult_add_bkp2" for hierarchy "mulfactor:inst3|fmta:mul_a|altmult_add:ALTMULT_ADD_component|mult_add_bkp2:auto_generated"
Info: Elaborating entity "rofactor" for hierarchy "rofactor:inst"
Info: Elaborating entity "cfft4" for hierarchy "cfft4:inst9"
Info: Elaborating entity "fft_data_buf" for hierarchy "fft_data_buf:inst7"
Info: Found 1 design units, including 1 entities, in source file ../quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Error: Cannot use value BYPASS of parameter CLOCK_ENABLE_INPUT_A with device family Stratix in altsyncram megafunction File: E:/altera/71/radix4_256fft/fft_data_buf.v Line: 80
Error: Cannot use value BYPASS of parameter CLOCK_ENABLE_INPUT_B with device family Stratix in altsyncram megafunction File: E:/altera/71/radix4_256fft/fft_data_buf.v Line: 80
Error: Cannot use value BYPASS of parameter CLOCK_ENABLE_OUTPUT_A with device family Stratix in altsyncram megafunction File: E:/altera/71/radix4_256fft/fft_data_buf.v Line: 80
Error: Cannot use value BYPASS of parameter CLOCK_ENABLE_OUTPUT_B with device family Stratix in altsyncram megafunction File: E:/altera/71/radix4_256fft/fft_data_buf.v Line: 80
Info: Elaborating entity "altsyncram" for hierarchy "fft_data_buf:inst7|altsyncram:altsyncram_component"
Error: Can't elaborate user hierarchy "fft_data_buf:inst7|altsyncram:altsyncram_component" File: E:/altera/71/radix4_256fft/fft_data_buf.v Line: 80
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
    Info: Allocated 151 megabytes of memory during processing
    Error: Processing ended: Fri Feb 22 17:48:08 2008
    Error: Elapsed time: 00:00:08