cfft4.v

基于VHDL语言的一个FFT快速傅里叶变换程序采用4蝶形算法

/*
 * filename: cfft4.v
 *
 * version: 2007-04-21
 *
 * funciton: 基4蝶型运算.采用流水线设计,连续输入连续输出.
 *     输出比输入延伸了6个时钟.
 *
 */

module cfft4
(
	clk8x,
	rst,
	cfft4en,
	I,
	Q,

	Iout,
	Qout
);

parameter				WIDTH=16;

input					clk8x, rst, cfft4en;
input	[WIDTH-1:0]		I, Q;

output	[WIDTH-1:0]		Iout, Qout;

wire	[WIDTH+1:0]		Ie, Qe;
reg		[2:0]			cnt8;
reg						outen;

reg		[WIDTH+1:0]  	rAI_3, rAI_2, rAI_1, rAI_0, rBI_3, rBI_2, rBI_1, rBI_0,
						rAQ_3, rAQ_2, rAQ_1, rAQ_0, rBQ_3, rBQ_2, rBQ_1, rBQ_0,
						Ieo, Qeo;

assign Ie = {I[WIDTH-1], I[WIDTH-1], I};
assign Qe = {Q[WIDTH-1], Q[WIDTH-1], Q};

always @ (posedge clk8x)
begin
	if (rst)
		cnt8 <= 3'b000;
	else if (cfft4en || outen)
		cnt8 <= cnt8 + 1'b1;
	else
		cnt8 <= 3'b000;

	if (rst)
		outen <= 1'b0;
	else if (cnt8 == 5)
		outen <= cfft4en;
end

//-------------------------------------------------------------------------
////// in: A    out: B     reg: rA, rB                                   --
// 0 rA[0]<=A0 rB[1]<=rA[0]-rA[2] rB[2]<=rA[1]+rA[3]    B3<=rB[1]-rB[3]  --
// 1 rA[1]<=A1 rB[3]<=(-j)*(rA[1]-rA[3])                B0<=rB[0]+rB[2]  --
// 2 rA[2]<=A2                                          B1<=rB[1]+rB[3]  --
// 3 rA[3]<=A3 rB[0]<=rA[0]+rA[2]                       B2<=rB[0]-rB[2]  --
//-------------------------------------------------------------------------
// 数据连续输入,延时6个时钟后连续输出
always @ (posedge clk8x)
begin
	case (cnt8[1:0])
	2'b00:	begin
			rAI_0 <= cfft4en ? Ie : 18'b0;
			rAQ_0 <= cfft4en ? Qe : 18'b0;
			rBI_1 <= rAI_0-rAI_2;
			rBQ_1 <= rAQ_0-rAQ_2;
			rBI_2 <= rAI_1+rAI_3;
			rBQ_2 <= rAQ_1+rAQ_3;
			Ieo <= rBI_1-rBI_3;
			Qeo <= rBQ_1-rBQ_3;
			end
	2'b01:	begin
			rAI_1 <= cfft4en ? Ie : 18'b0;
			rAQ_1 <= cfft4en ? Qe : 18'b0;
			rBI_3 <= rAQ_1-rAQ_3;
			rBQ_3 <= rAI_3-rAI_1;
			Ieo <= rBI_0+rBI_2;
			Qeo <= rBQ_0+rBQ_2;
			end
	2'b10:	begin
			rAI_2 <= cfft4en ? Ie : 18'b0;
			rAQ_2 <= cfft4en ? Qe : 18'b0;
			Ieo <= rBI_1+rBI_3;
			Qeo <= rBQ_1+rBQ_3;
			end
	2'b11:  begin
			rAI_3 <= cfft4en ? Ie : 18'b0;
			rAQ_3 <= cfft4en ? Qe : 18'b0;
			rBI_0 <= rAI_0+rAI_2;
			rBQ_0 <= rAQ_0+rAQ_2;
			Ieo <= rBI_0-rBI_2;
			Qeo <= rBQ_0-rBQ_2;
			end
	endcase
end

assign Iout = Ieo[WIDTH+1:2];
assign Qout = Qeo[WIDTH+1:2];

endmodule