mult_add_clp2.tdf

基于VHDL语言的一个FFT快速傅里叶变换程序采用4蝶形算法

--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Stratix" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_A1="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_REGISTER_B1="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_A1="DATAA" INPUT_SOURCE_B0="DATAB" INPUT_SOURCE_B1="DATAB" MULTIPLIER1_DIRECTION="SUB" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=33 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 7.1 cbx_alt_ded_mult_y 2007:03:06:10:54:52:SJ cbx_altmult_add 2007:03:23:15:31:46:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_mult 2007:03:30:15:38:08:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_padd 2006:11:07:15:06:12:SJ cbx_parallel_add 2007:01:30:03:53:08:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


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FUNCTION stratix_mac_mult (aclr[3..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], ena[3..0], signa, signb)
WITH ( 	dataa_clear,	dataa_clock,	dataa_width,	datab_clear,	datab_clock,	datab_width,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_internally_grounded,	signb_clear,	signb_clock,	signb_internally_grounded) 
RETURNS ( dataout[dataa_width+datab_width-1..0], scanouta[dataa_width-1..0], scanoutb[datab_width-1..0]);
PARAMETERS
(
	dataa_width = 1,
	datab_width = 1,
	datac_width = 1,
	datad_width = 1,
	dataout_width = 72
);
FUNCTION stratix_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], datac[datac_width-1..0], datad[datad_width-1..0], ena[3..0], signa, signb, zeroacc)
WITH ( 	addnsub0_clear,	addnsub0_clock,	addnsub0_pipeline_clear,	addnsub0_pipeline_clock,	addnsub1_clear,	addnsub1_clock,	addnsub1_pipeline_clear,	addnsub1_pipeline_clock,	dataa_width,	datab_width,	datac_width,	datad_width,	dataout_width,	operation_mode,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_pipeline_clear,	signa_pipeline_clock,	signb_clear,	signb_clock,	signb_pipeline_clear,	signb_pipeline_clock,	zeroacc_clear,	zeroacc_clock,	zeroacc_pipeline_clear,	zeroacc_pipeline_clock) 
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 4 
SUBDESIGN mult_add_clp2
( 
	clock0	:	input;
	dataa[31..0]	:	input;
	datab[31..0]	:	input;
	result[32..0]	:	output;
) 
VARIABLE 
	mac_mult1 : stratix_mac_mult
		WITH (
			dataa_width = 16,
			datab_width = 16,
			output_clear = "3",
			output_clock = "0"
		);
	mac_mult2 : stratix_mac_mult
		WITH (
			dataa_width = 16,
			datab_width = 16,
			output_clear = "3",
			output_clock = "0"
		);
	mac_out3 : stratix_mac_out
		WITH (
			dataa_width = 32,
			datab_width = 32,
			dataout_width = 72,
			operation_mode = "one_level_adder"
		);
	aclr0	: NODE;
	aclr1	: NODE;
	aclr2	: NODE;
	aclr3	: NODE;
	clock1	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	dataa_bus[31..0]	: WIRE;
	datab_bus[31..0]	: WIRE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( dataa_bus[15..0]);
	mac_mult1.datab[] = ( datab_bus[15..0]);
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"1";
	mac_mult1.signb = B"1";
	mac_mult2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult2.dataa[] = ( dataa_bus[31..16]);
	mac_mult2.datab[] = ( datab_bus[31..16]);
	mac_mult2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult2.signa = B"1";
	mac_mult2.signb = B"1";
	mac_out3.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out3.addnsub0 = B"0";
	mac_out3.addnsub1 = B"1";
	mac_out3.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out3.dataa[] = ( mac_mult1.dataout[31..0]);
	mac_out3.datab[] = ( mac_mult2.dataout[31..0]);
	mac_out3.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out3.signa = B"1";
	mac_out3.signb = B"1";
	aclr0 = GND;
	aclr1 = GND;
	aclr2 = GND;
	aclr3 = GND;
	clock1 = VCC;
	clock2 = VCC;
	clock3 = VCC;
	dataa_bus[] = ( dataa[31..0]);
	datab_bus[] = ( datab[31..0]);
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	result[32..0] = mac_out3.dataout[32..0];
END;
--VALID FILE