addr_gen.v

基于VHDL语言的一个FFT快速傅里叶变换程序采用4蝶形算法

/*
 * filename: addr_gen.v
 *
 * version: 2007-04-21
 *
 * funciton: 读写地址生成和控制模块.
 *
 */

module	addr_gen
(
	rst,
	fft_start,
	clk8x,
	invert,
	I_in,
	Q_in,
	fft_I,
	fft_Q,

	wren,
	out_start,
	outen,
	cfft4en,
	rof_start,
	rdaddr,
	wraddr,
	wdataI,
	wdataQ
);

parameter				WIDTH = 16;
parameter				FFT_LOOP_DELAY = 4'b1011;
	// FFT_LOOP_DELAY = ADDRGEN_DELAY+RAM_DELAY+CFFT4_DELAY+MUL_DELAY+DIV_DELAY
//parameter				ADDRGEN_DELAY = 1'b1;
parameter				RAM_DELAY = 1'b1;
parameter				CFFT4_DELAY = 3'b110;
parameter				ROFACTOR_DELAY = 1'b1;
//parameter				MUL_DELAY = 2'b10;
//parameter				DIV_DELAY = 1'b1;

input					rst, fft_start, clk8x, invert;
input	[WIDTH-1:0]		I_in, Q_in, fft_I, fft_Q;

output					wren, cfft4en, rof_start, out_start, outen;
output	[7:0]			rdaddr, wraddr;
output	[WIDTH-1:0]		wdataI, wdataQ;


reg		[2:0]			wrstate,rdstate;
reg		[7:0]			wrcnt, rdcnt, wraddr, rdaddr;
reg						wren, out_start, outen, cfft4en, rof_start;
reg		[WIDTH-1:0]		wdataI, wdataQ;

//////////////////////////////////////////////////////
// write process
always @ (posedge clk8x)
begin
	if (rst)
		wrstate <= 3'b0;
	else if (fft_start)
		wrstate <= 3'b001;
	else if (wrcnt == 255)
	begin
		if (wrstate == 5)
			wrstate <= 3'b0;
		else
			wrstate <= wrstate +1'b1;
	end

	if (rst || wrstate==0)
		wren <= 1'b0;
	else
		wren <= 1'b1;
end

always @ (posedge clk8x)
begin

	if (rst || wrstate==0)
		wrcnt <= 8'b0;
	else
		wrcnt <= wrcnt + 1'b1;

	case (wrstate)
		3'b001 : wraddr <= wrcnt;
		3'b010 : wraddr <= {wrcnt[1:0], wrcnt[7:2]};
		3'b011 : wraddr <= {wrcnt[7:6], wrcnt[1:0], wrcnt[5:2]};
		3'b100 : wraddr <= {wrcnt[7:4], wrcnt[1:0], wrcnt[3:2]};
		3'b101 : wraddr <= wrcnt;
		default : wraddr <= 8'b0;
	endcase
end

always @ (posedge clk8x)
begin
	if (rst || wrstate==0)
		{wdataQ, wdataI} <= 32'b0;
	else if (wrstate == 1)
	begin
		wdataQ <= invert ? -Q_in : Q_in;
		wdataI <= I_in;
	end
	else if (wrstate == 5)
	begin
		wdataQ <= invert ? -fft_Q : fft_Q;
		wdataI <= fft_I;
	end
	else
		{wdataQ, wdataI} <= {fft_Q, fft_I};
end

/////////////////////////////////////////////////////////
// read process
always @ (posedge clk8x)
begin
	if (rst)
		rdstate <= 3'b0;
	else if (wrstate==1 && wrcnt==8'hff-FFT_LOOP_DELAY)
		rdstate <= 3'b001;
	else if (rdcnt == 255)
	begin
		if (rdstate == 5)
			rdstate <= 3'b0;
		else
			rdstate <= rdstate +1'b1;
	end
end

always @ (posedge clk8x)
begin

	if (rst)
		rdcnt <= 8'b0;
	else if (rdstate==0 && ~outen)
		rdcnt <= 8'b0;
	else
		rdcnt <= rdcnt + 1'b1;

	case (rdstate)
		3'b001 : rdaddr <= {rdcnt[1:0], rdcnt[7:2]};
		3'b010 : rdaddr <= {rdcnt[7:6], rdcnt[1:0], rdcnt[5:2]};
		3'b011 : rdaddr <= {rdcnt[7:4], rdcnt[1:0], rdcnt[3:2]};
		3'b100 : rdaddr <= rdcnt;
		3'b101 : rdaddr <= {rdcnt[1:0], rdcnt[3:2], rdcnt[5:4], rdcnt[7:6]};
		default : rdaddr <= 8'b0;
	endcase
end

///////////////////////////////////////////////////////////
// control signal generate
always @ (posedge clk8x)
begin
	if (rst)
		cfft4en <= 1'b0;
	else if (rdstate==1 && rdcnt==RAM_DELAY)
		cfft4en <= 1'b1;
	else if (rdstate==5 && rdcnt==RAM_DELAY)
		cfft4en <= 1'b0;

	if (rst)
		rof_start <= 1'b0;
	else if (rdstate==1 && rdcnt==RAM_DELAY+CFFT4_DELAY-ROFACTOR_DELAY)
		rof_start <= 1'b1;
	else
		rof_start <= 1'b0;

	if (rst)
		outen <= 1'b0;
	else if (rdcnt==RAM_DELAY)
	begin
		if (rdstate==5)
			outen <= 1'b1;
		else
			outen <= 1'b0;
	end

	if (rst)
		out_start <= 1'b0;
	else if (rdstate==5 && rdcnt==RAM_DELAY-1)
		out_start <= 1'b1;
	else
		out_start <= 1'b0;
end

endmodule