prev_cmp_lcd_1602.fit.qmsg

基于FPGA的LCD1602显示

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.953 ns register register " "Info: Estimated most critical path is register to register delay of 4.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|div_reg\[11\] 1 REG LAB_X2_Y2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y2; Fanout = 3; REG Node = 'lcd:inst\|div_reg\[11\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|div_reg[11] } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(0.202 ns) 1.592 ns lcd:inst\|LessThan0~340 2 COMB LAB_X2_Y3 1 " "Info: 2: + IC(1.390 ns) + CELL(0.202 ns) = 1.592 ns; Loc. = LAB_X2_Y3; Fanout = 1; COMB Node = 'lcd:inst\|LessThan0~340'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { lcd:inst|div_reg[11] lcd:inst|LessThan0~340 } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 2.403 ns lcd:inst\|LessThan0~341 3 COMB LAB_X2_Y3 1 " "Info: 3: + IC(0.605 ns) + CELL(0.206 ns) = 2.403 ns; Loc. = LAB_X2_Y3; Fanout = 1; COMB Node = 'lcd:inst\|LessThan0~341'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { lcd:inst|LessThan0~340 lcd:inst|LessThan0~341 } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 3.214 ns lcd:inst\|LessThan0~343 4 COMB LAB_X2_Y3 22 " "Info: 4: + IC(0.441 ns) + CELL(0.370 ns) = 3.214 ns; Loc. = LAB_X2_Y3; Fanout = 22; COMB Node = 'lcd:inst\|LessThan0~343'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { lcd:inst|LessThan0~341 lcd:inst|LessThan0~343 } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.660 ns) 4.953 ns lcd:inst\|div_reg\[15\] 5 REG LAB_X2_Y2 3 " "Info: 5: + IC(1.079 ns) + CELL(0.660 ns) = 4.953 ns; Loc. = LAB_X2_Y2; Fanout = 3; REG Node = 'lcd:inst\|div_reg\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.739 ns" { lcd:inst|LessThan0~343 lcd:inst|div_reg[15] } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.438 ns ( 29.03 % ) " "Info: Total cell delay = 1.438 ns ( 29.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.515 ns ( 70.97 % ) " "Info: Total interconnect delay = 3.515 ns ( 70.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.953 ns" { lcd:inst|div_reg[11] lcd:inst|LessThan0~340 lcd:inst|LessThan0~341 lcd:inst|LessThan0~343 lcd:inst|div_reg[15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X13_Y14 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "13 " "Warning: Found 13 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd1602_e 0 " "Info: Pin \"lcd1602_e\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_CE 0 " "Info: Pin \"FLASH_CE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "rtl8019_cs 0 " "Info: Pin \"rtl8019_cs\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_ADDR0 0 " "Info: Pin \"FLASH_ADDR0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_ADDR1 0 " "Info: Pin \"FLASH_ADDR1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[7\] 0 " "Info: Pin \"FLASH_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[6\] 0 " "Info: Pin \"FLASH_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[5\] 0 " "Info: Pin \"FLASH_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[4\] 0 " "Info: Pin \"FLASH_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[3\] 0 " "Info: Pin \"FLASH_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[2\] 0 " "Info: Pin \"FLASH_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[1\] 0 " "Info: Pin \"FLASH_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FLASH_DQ\[0\] 0 " "Info: Pin \"FLASH_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "12 " "Warning: Following 12 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_CE VCC " "Info: Pin FLASH_CE has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_CE } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_CE" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 208 328 504 224 "FLASH_CE" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_CE } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_CE } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "rtl8019_cs VCC " "Info: Pin rtl8019_cs has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { rtl8019_cs } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl8019_cs" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 232 328 504 248 "rtl8019_cs" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rtl8019_cs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rtl8019_cs } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_ADDR0 GND " "Info: Pin FLASH_ADDR0 has GND driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_ADDR0 } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_ADDR0" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 64 488 664 80 "FLASH_ADDR0" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_ADDR0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_ADDR0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_ADDR1 VCC " "Info: Pin FLASH_ADDR1 has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_ADDR1 } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_ADDR1" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 80 488 664 96 "FLASH_ADDR1" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_ADDR1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_ADDR1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[7\] GND " "Info: Pin FLASH_DQ\[7\] has GND driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[7] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[7\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[6\] VCC " "Info: Pin FLASH_DQ\[6\] has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[6] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[6\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[5\] GND " "Info: Pin FLASH_DQ\[5\] has GND driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[5] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[5\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[4\] VCC " "Info: Pin FLASH_DQ\[4\] has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[4] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[4\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[3\] GND " "Info: Pin FLASH_DQ\[3\] has GND driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[3] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[3\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[2\] VCC " "Info: Pin FLASH_DQ\[2\] has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[2] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[2\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[1\] VCC " "Info: Pin FLASH_DQ\[1\] has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[1] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[1\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_DQ\[0\] VCC " "Info: Pin FLASH_DQ\[0\] has VCC driving its datain port" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { FLASH_DQ[0] } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FLASH_DQ\[0\]" } } } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 96 488 666 112 "FLASH_DQ\[7..0\]" "" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FLASH_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/lcd_1602_v/lcd_1602.fit.smsg " "Info: Generated suppressed messages file D:/lcd_1602_v/lcd_1602.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 16 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 10 16:21:11 2009 " "Info: Processing ended: Sat Jan 10 16:21:11 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}