prev_cmp_lcd_1602.qmsg

基于FPGA的LCD1602显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 10 16:24:32 2009 " "Info: Processing started: Sat Jan 10 16:24:32 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_1602 -c lcd_1602 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_1602 -c lcd_1602" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_1602.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_1602.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_1602 " "Info: Found entity 1: lcd_1602" {  } { { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "' lcd.v(184) " "Error (10170): Verilog HDL syntax error at lcd.v(184) near text '" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 184 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"'\";  expecting \"@\", or an identifier, or a number, or a system task, or \"(\", or \"\{\", or unary operator lcd.v(184) " "Error (10170): Verilog HDL syntax error at lcd.v(184) near text \"'\";  expecting \"@\", or an identifier, or a number, or a system task, or \"(\", or \"\{\", or unary operator" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 184 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lcd lcd.v(1) " "Error (10112): Ignored design unit \"lcd\" at lcd.v(1) due to previous errors" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 1 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file lcd.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "char_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file char_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_ram-fun " "Info: Found design unit 1: char_ram-fun" {  } { { "char_ram.vhd" "" { Text "D:/lcd_1602_v/char_ram.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 char_ram " "Info: Found entity 1: char_ram" {  } { { "char_ram.vhd" "" { Text "D:/lcd_1602_v/char_ram.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat Jan 10 16:24:34 2009 " "Error: Processing ended: Sat Jan 10 16:24:34 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}