prev_cmp_lcd_1602.tan.qmsg

基于FPGA的LCD1602显示

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst\|div_reg\[12\] register lcd:inst\|div_reg\[15\] 210.39 MHz 4.753 ns Internal " "Info: Clock \"clk\" has Internal fmax of 210.39 MHz between source register \"lcd:inst\|div_reg\[12\]\" and destination register \"lcd:inst\|div_reg\[15\]\" (period= 4.753 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.489 ns + Longest register register " "Info: + Longest register to register delay is 4.489 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|div_reg\[12\] 1 REG LCFF_X2_Y2_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y2_N5; Fanout = 3; REG Node = 'lcd:inst\|div_reg\[12\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|div_reg[12] } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.140 ns) + CELL(0.370 ns) 1.510 ns lcd:inst\|LessThan0~339 2 COMB LCCOMB_X2_Y3_N4 1 " "Info: 2: + IC(1.140 ns) + CELL(0.370 ns) = 1.510 ns; Loc. = LCCOMB_X2_Y3_N4; Fanout = 1; COMB Node = 'lcd:inst\|LessThan0~339'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { lcd:inst|div_reg[12] lcd:inst|LessThan0~339 } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.370 ns) 2.254 ns lcd:inst\|LessThan0~341 3 COMB LCCOMB_X2_Y3_N2 1 " "Info: 3: + IC(0.374 ns) + CELL(0.370 ns) = 2.254 ns; Loc. = LCCOMB_X2_Y3_N2; Fanout = 1; COMB Node = 'lcd:inst\|LessThan0~341'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.744 ns" { lcd:inst|LessThan0~339 lcd:inst|LessThan0~341 } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 2.822 ns lcd:inst\|LessThan0~343 4 COMB LCCOMB_X2_Y3_N0 22 " "Info: 4: + IC(0.362 ns) + CELL(0.206 ns) = 2.822 ns; Loc. = LCCOMB_X2_Y3_N0; Fanout = 22; COMB Node = 'lcd:inst\|LessThan0~343'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { lcd:inst|LessThan0~341 lcd:inst|LessThan0~343 } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.660 ns) 4.489 ns lcd:inst\|div_reg\[15\] 5 REG LCFF_X2_Y2_N11 3 " "Info: 5: + IC(1.007 ns) + CELL(0.660 ns) = 4.489 ns; Loc. = LCFF_X2_Y2_N11; Fanout = 3; REG Node = 'lcd:inst\|div_reg\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.667 ns" { lcd:inst|LessThan0~343 lcd:inst|div_reg[15] } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.606 ns ( 35.78 % ) " "Info: Total cell delay = 1.606 ns ( 35.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.883 ns ( 64.22 % ) " "Info: Total interconnect delay = 2.883 ns ( 64.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.489 ns" { lcd:inst|div_reg[12] lcd:inst|LessThan0~339 lcd:inst|LessThan0~341 lcd:inst|LessThan0~343 lcd:inst|div_reg[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.489 ns" { lcd:inst|div_reg[12] {} lcd:inst|LessThan0~339 {} lcd:inst|LessThan0~341 {} lcd:inst|LessThan0~343 {} lcd:inst|div_reg[15] {} } { 0.000ns 1.140ns 0.374ns 0.362ns 1.007ns } { 0.000ns 0.370ns 0.370ns 0.206ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 23 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 23; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 2.782 ns lcd:inst\|div_reg\[15\] 3 REG LCFF_X2_Y2_N11 3 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N11; Fanout = 3; REG Node = 'lcd:inst\|div_reg\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { clk~clkctrl lcd:inst|div_reg[15] } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.92 % ) " "Info: Total cell delay = 1.806 ns ( 64.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 35.08 % ) " "Info: Total interconnect delay = 0.976 ns ( 35.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|div_reg[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|div_reg[15] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 23 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 23; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 2.782 ns lcd:inst\|div_reg\[12\] 3 REG LCFF_X2_Y2_N5 3 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N5; Fanout = 3; REG Node = 'lcd:inst\|div_reg\[12\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { clk~clkctrl lcd:inst|div_reg[12] } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.92 % ) " "Info: Total cell delay = 1.806 ns ( 64.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 35.08 % ) " "Info: Total interconnect delay = 0.976 ns ( 35.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|div_reg[12] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|div_reg[12] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|div_reg[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|div_reg[15] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|div_reg[12] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|div_reg[12] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 75 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.489 ns" { lcd:inst|div_reg[12] lcd:inst|LessThan0~339 lcd:inst|LessThan0~341 lcd:inst|LessThan0~343 lcd:inst|div_reg[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.489 ns" { lcd:inst|div_reg[12] {} lcd:inst|LessThan0~339 {} lcd:inst|LessThan0~341 {} lcd:inst|LessThan0~343 {} lcd:inst|div_reg[15] {} } { 0.000ns 1.140ns 0.374ns 0.362ns 1.007ns } { 0.000ns 0.370ns 0.370ns 0.206ns 0.660ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|div_reg[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|div_reg[15] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|div_reg[12] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|div_reg[12] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lcd1602_e lcd:inst\|clk_int 9.593 ns register " "Info: tco from clock \"clk\" to destination pin \"lcd1602_e\" through register \"lcd:inst\|clk_int\" is 9.593 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 23 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 23; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 2.782 ns lcd:inst\|clk_int 3 REG LCFF_X2_Y2_N29 1 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N29; Fanout = 1; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { clk~clkctrl lcd:inst|clk_int } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.92 % ) " "Info: Total cell delay = 1.806 ns ( 64.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 35.08 % ) " "Info: Total interconnect delay = 0.976 ns ( 35.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 87 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.507 ns + Longest register pin " "Info: + Longest register to pin delay is 6.507 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|clk_int 1 REG LCFF_X2_Y2_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y2_N29; Fanout = 1; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|clk_int } "NODE_NAME" } } { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.211 ns) + CELL(3.296 ns) 6.507 ns lcd1602_e 2 PIN PIN_163 0 " "Info: 2: + IC(3.211 ns) + CELL(3.296 ns) = 6.507 ns; Loc. = PIN_163; Fanout = 0; PIN Node = 'lcd1602_e'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.507 ns" { lcd:inst|clk_int lcd1602_e } "NODE_NAME" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 48 488 664 64 "lcd1602_e" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.296 ns ( 50.65 % ) " "Info: Total cell delay = 3.296 ns ( 50.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.211 ns ( 49.35 % ) " "Info: Total interconnect delay = 3.211 ns ( 49.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.507 ns" { lcd:inst|clk_int lcd1602_e } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.507 ns" { lcd:inst|clk_int {} lcd1602_e {} } { 0.000ns 3.211ns } { 0.000ns 3.296ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl lcd:inst|clk_int } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} lcd:inst|clk_int {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.507 ns" { lcd:inst|clk_int lcd1602_e } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.507 ns" { lcd:inst|clk_int {} lcd1602_e {} } { 0.000ns 3.211ns } { 0.000ns 3.296ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 10 16:21:15 2009 " "Info: Processing ended: Sat Jan 10 16:21:15 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}