lcd_1602.map.qmsg

基于FPGA的LCD1602显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 10 16:27:19 2009 " "Info: Processing started: Sat Jan 10 16:27:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_1602 -c lcd_1602 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_1602 -c lcd_1602" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_1602.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_1602.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_1602 " "Info: Found entity 1: lcd_1602" {  } { { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "char_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file char_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_ram-fun " "Info: Found design unit 1: char_ram-fun" {  } { { "char_ram.vhd" "" { Text "D:/lcd_1602_v/char_ram.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 char_ram " "Info: Found entity 1: char_ram" {  } { { "char_ram.vhd" "" { Text "D:/lcd_1602_v/char_ram.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_1602 " "Info: Elaborating entity \"lcd_1602\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "lcd_1602 " "Warning: Processing legacy GDF or BDF entity \"lcd_1602\" with Max+Plus II bus and instance naming rules" {  } { { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst\"" {  } { { "lcd_1602.bdf" "inst" { Schematic "D:/lcd_1602_v/lcd_1602.bdf" { { 24 288 400 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "state lcd.v(9) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(9): object \"state\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 9 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag lcd.v(10) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(10): object \"flag\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 10 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "counter lcd.v(12) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(12): object \"counter\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 12 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "divcounter lcd.v(13) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(13): object \"divcounter\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 13 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "address lcd.v(96) " "Warning (10240): Verilog HDL Always Construct warning at lcd.v(96): inferring latch(es) for variable \"address\", which holds its previous value in one or more paths through the always construct" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "address\[0\] lcd.v(96) " "Info (10041): Inferred latch for \"address\[0\]\" at lcd.v(96)" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "address\[1\] lcd.v(96) " "Info (10041): Inferred latch for \"address\[1\]\" at lcd.v(96)" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "address\[2\] lcd.v(96) " "Info (10041): Inferred latch for \"address\[2\]\" at lcd.v(96)" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "address\[3\] lcd.v(96) " "Info (10041): Inferred latch for \"address\[3\]\" at lcd.v(96)" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "address\[4\] lcd.v(96) " "Info (10041): Inferred latch for \"address\[4\]\" at lcd.v(96)" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "address\[5\] lcd.v(96) " "Info (10041): Inferred latch for \"address\[5\]\" at lcd.v(96)" {  } { { "lcd.v" "" { Text "D:/lcd_1602_v/lcd.v" 96 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "char_ram lcd:inst\|char_ram:charram " "Info: Elaborating entity \"char_ram\" for hierarchy \"lcd:inst\|char_ram:charram\"" {  } { { "lcd.v" "charram" { Text "D:/lcd_1602_v/lcd.v" 190 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}