📄 fifo.map.rpt
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; Total registers ; 9 ;
; -- Dedicated logic registers ; 9 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 21 ;
; Total memory bits ; 128 ;
; Maximum fan-out node ; wren~input ;
; Maximum fan-out ; 13 ;
; Total fan-out ; 195 ;
; Average fan-out ; 2.71 ;
+---------------------------------------------+------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------+--------------+
; |fifo ; 13 (13) ; 9 (9) ; 128 ; 0 ; 0 ; 0 ; 21 ; 0 ; |fifo ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fifo|altsyncram:altsyncram_component ; work ;
; |altsyncram_0un1:auto_generated| ; 0 (0) ; 0 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fifo|altsyncram:altsyncram_component|altsyncram_0un1:auto_generated ; work ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 8 ; 16 ; 8 ; 128 ; None ;
+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 9 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 9 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; subempty ; 6 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+---------------------------------------------------------------------------------------+
; Source assignments for altsyncram:altsyncram_component|altsyncram_0un1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------+
+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 4 ; Signed Integer ;
; NUMWORDS_A ; 16 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Signed Integer ;
; WIDTHAD_B ; 4 ; Signed Integer ;
; NUMWORDS_B ; 16 ; Signed Integer ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; CLOCK1 ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone III ; Untyped ;
; CBXI_PARAMETER ; altsyncram_0un1 ; Untyped ;
+------------------------------------+----------------------+------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Wed Jun 18 16:22:19 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo -c fifo
Info: Found 2 design units, including 1 entities, in source file test.vhd
Info: Found design unit 1: test-SYN
Info: Found entity 1: test
Warning: Using design file fifo.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: fifo-SYN
Info: Found entity 1: fifo
Info: Elaborating entity "fifo" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_0un1.tdf
Info: Found entity 1: altsyncram_0un1
Info: Elaborating entity "altsyncram_0un1" for hierarchy "altsyncram:altsyncram_component|altsyncram_0un1:auto_generated"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 63 device resources after synthesis - the final resource count might be different
Info: Implemented 12 input pins
Info: Implemented 9 output pins
Info: Implemented 13 logic cells
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 175 megabytes of memory during processing
Info: Processing ended: Wed Jun 18 16:22:23 2008
Info: Elapsed time: 00:00:04
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