fifo.vhd

TCC221图像传感器和FPGA实现图像采集

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY altera_mf;
USE altera_mf.all;

ENTITY fifo IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdclock		: IN STD_LOGIC ;
		wrclock		: IN STD_LOGIC ;
		q		    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		empty       :out std_logic;-- high leave is valid
        wren        :in  std_logic;
		clr         :in  std_logic
	);
END fifo;


ARCHITECTURE SYN OF fifo IS

	SIGNAL sub_wire0	:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL pw           :std_logic_vector(3 downto 0);
    signal pr           :std_logic_vector(3 downto 0);
    signal subempty     :std_logic;
    --signal wren         :std_logic:='0';

	COMPONENT altsyncram
	GENERIC (
		address_aclr_b		: STRING;
		address_reg_b		: STRING;
		clock_enable_input_a		: STRING;
		clock_enable_input_b		: STRING;
		clock_enable_output_b		: STRING;
		intended_device_family		: STRING;
		lpm_type		: STRING;
		numwords_a		: NATURAL;
		numwords_b		: NATURAL;
		operation_mode		: STRING;
		outdata_aclr_b		: STRING;
		outdata_reg_b		: STRING;
		power_up_uninitialized		: STRING;
		read_during_write_mode_mixed_ports		: STRING;
		widthad_a		: NATURAL;
		widthad_b		: NATURAL;
		width_a		: NATURAL;
		width_b		: NATURAL;
		width_byteena_a		: NATURAL
	);
	PORT (
			wren_a	: IN STD_LOGIC ;
			clock0	: IN STD_LOGIC ;
			clock1	: IN STD_LOGIC ;
			address_a	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
			address_b	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	q    <= sub_wire0(7 DOWNTO 0);
	altsyncram_component : altsyncram
	GENERIC MAP (
		address_aclr_b => "NONE",
		address_reg_b => "CLOCK1",
		clock_enable_input_a => "BYPASS",
		clock_enable_input_b => "BYPASS",
		clock_enable_output_b => "BYPASS",
		intended_device_family => "Cyclone III",
		lpm_type => "altsyncram",
		numwords_a => 16,
		numwords_b => 16,
		operation_mode => "DUAL_PORT",
		outdata_aclr_b => "NONE",
		outdata_reg_b => "CLOCK1",
		power_up_uninitialized => "FALSE",
		read_during_write_mode_mixed_ports => "DONT_CARE",
		widthad_a => 4,
		widthad_b => 4,
		width_a => 8,
		width_b => 8,
		width_byteena_a => 1
	)
	PORT MAP (
		wren_a => wren,
		clock0 => wrclock,
		clock1 => rdclock,
		address_a => pw,
		address_b => pr,
		data_a => data,
		q_b => sub_wire0
	);

    --wren<='1';
    empty<=subempty;
  
    process(clr,wrclock)
    begin
      if(clr='0') then
        pw<="0000";
        subempty<='1';
      elsif(wrclock'event and wrclock='1')then
          if(pr=pw)then
            subempty<='1';
          end if;         
          if(wren='1') then
            pw<=pw+1;
            subempty<='0';
         end if;
      end if;
    end process;
   
    process(clr,rdclock)
    begin
      if(clr='0')then
        pr<="0000";
      elsif(rdclock'event and rdclock='1')then
        if(subempty='0')then
          pr<=pr+"0001";
        end if;
      end if;
    end process;
        


END SYN;