📄 fifo.sta.rpt
字号:
; -1.857 ; 1.000 ; 2.857 ; Period ; rdclock ; Rise ; pr[2] ;
; -1.857 ; 1.000 ; 2.857 ; Period ; rdclock ; Rise ; pr[3] ;
; -1.857 ; 1.000 ; 2.857 ; Period ; wrclock ; Rise ; subempty ;
; -1.777 ; 1.000 ; 2.777 ; Period ; rdclock ; Rise ; rdclock ;
; -1.777 ; 1.000 ; 2.777 ; Period ; wrclock ; Rise ; wrclock ;
; 0.132 ; 0.350 ; 0.218 ; High ; wrclock ; Rise ; pw[0] ;
; 0.132 ; 0.350 ; 0.218 ; High ; wrclock ; Rise ; pw[1] ;
; 0.132 ; 0.350 ; 0.218 ; High ; wrclock ; Rise ; pw[2] ;
; 0.132 ; 0.350 ; 0.218 ; High ; wrclock ; Rise ; pw[3] ;
; 0.132 ; 0.350 ; 0.218 ; High ; wrclock ; Rise ; subempty ;
; 0.138 ; 0.356 ; 0.218 ; High ; rdclock ; Rise ; pr[0] ;
; 0.138 ; 0.356 ; 0.218 ; High ; rdclock ; Rise ; pr[1] ;
; 0.138 ; 0.356 ; 0.218 ; High ; rdclock ; Rise ; pr[2] ;
; 0.138 ; 0.356 ; 0.218 ; High ; rdclock ; Rise ; pr[3] ;
; 0.202 ; 0.439 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_re_reg ;
; 0.202 ; 0.439 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 0.202 ; 0.439 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg1 ;
; 0.202 ; 0.439 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg2 ;
; 0.202 ; 0.439 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg3 ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[2] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[0] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[1] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[3] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[4] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[5] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[6] ;
; 0.203 ; 0.440 ; 0.237 ; High ; rdclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[7] ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg4 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg1 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a1~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg2 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a2~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg3 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a3~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a4~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg5 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a5~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg6 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a6~porta_memory_reg0 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg7 ;
; 0.212 ; 0.449 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a7~porta_memory_reg0 ;
; 0.214 ; 0.451 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_we_reg ;
; 0.214 ; 0.451 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 0.214 ; 0.451 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg1 ;
; 0.214 ; 0.451 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg2 ;
; 0.214 ; 0.451 ; 0.237 ; High ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg3 ;
; 0.280 ; 0.517 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_we_reg ;
; 0.280 ; 0.517 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 0.280 ; 0.517 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg1 ;
; 0.280 ; 0.517 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg2 ;
; 0.280 ; 0.517 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg3 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg4 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg1 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a1~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg2 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a2~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg3 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a3~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a4~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg5 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a5~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg6 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a6~porta_memory_reg0 ;
; 0.282 ; 0.519 ; 0.237 ; Low ; wrclock ; Rise ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg7 ;
+--------+--------------+----------------+--------+---------+------------+------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; rdclock ; rdclock ; 54 ; 0 ; 0 ; 0 ;
; wrclock ; rdclock ; 4 ; 0 ; 0 ; 0 ;
; rdclock ; wrclock ; 4 ; 0 ; 0 ; 0 ;
; wrclock ; wrclock ; 27 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; rdclock ; rdclock ; 54 ; 0 ; 0 ; 0 ;
; wrclock ; rdclock ; 4 ; 0 ; 0 ; 0 ;
; rdclock ; wrclock ; 4 ; 0 ; 0 ; 0 ;
; wrclock ; wrclock ; 27 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 10 ; 10 ;
; Unconstrained Input Port Paths ; 23 ; 23 ;
; Unconstrained Output Ports ; 9 ; 9 ;
; Unconstrained Output Port Paths ; 9 ; 9 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Wed Jun 18 16:23:02 2008
Info: Command: quartus_sta fifo -c fifo
Info: qsta_default_script.tcl version: 24.0.1.7
Critical Warning: SDC file not found: 'fifo.sdc'
Info: No base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
Info: create_clock -period 1.000 -waveform {0.000 0.500} -name rdclock rdclock
Info: create_clock -period 1.000 -waveform {0.000 0.500} -name wrclock wrclock
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -2.987
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -2.987 -26.242 rdclock
Info: -1.129 -2.625 wrclock
Info: Worst-case hold slack is 0.530
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.530 0.000 wrclock
Info: 0.550 0.000 rdclock
Info: No recovery paths to report
Info: No removal paths to report
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
Info: Allocated 129 megabytes of memory during processing
Info: Processing ended: Wed Jun 18 16:23:04 2008
Info: Elapsed time: 00:00:02
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