fifo.sta.rpt

TCC221图像传感器和FPGA实现图像采集

TimeQuest Timing Analyzer report for fifo
Wed Jun 18 16:23:04 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Fmax Summary
  5. Setup Summary
  6. Hold Summary
  7. Recovery Summary
  8. Removal Summary
  9. Minimum Pulse Width
 10. Setup Transfers
 11. Hold Transfers
 12. Unconstrained Paths
 13. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                     ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name      ; fifo                                             ;
; Device Family      ; Cyclone III                                      ;
; Device Name        ; EP3C25E144C8                                     ;
; Timing Models      ; Preliminary                                      ;
; Delay Model        ; Slow Model                                       ;
; Rise/Fall Delays   ; Enabled                                          ;
+--------------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                 ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
; Clock Name ; Type ; Period ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets     ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
; rdclock    ; Base ; 1.000  ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { rdclock } ;
; wrclock    ; Base ; 1.000  ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { wrclock } ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+


+-------------------------+
; Fmax Summary            ;
+------------+------------+
; Fmax (MHz) ; Clock Name ;
+------------+------------+
; 250.82     ; rdclock    ;
; 469.7      ; wrclock    ;
+------------+------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------+
; Setup Summary                    ;
+---------+--------+---------------+
; Clock   ; Slack  ; End Point TNS ;
+---------+--------+---------------+
; rdclock ; -2.987 ; -26.242       ;
; wrclock ; -1.129 ; -2.625        ;
+---------+--------+---------------+


+---------------------------------+
; Hold Summary                    ;
+---------+-------+---------------+
; Clock   ; Slack ; End Point TNS ;
+---------+-------+---------------+
; wrclock ; 0.530 ; 0.000         ;
; rdclock ; 0.550 ; 0.000         ;
+---------+-------+---------------+


--------------------
; Recovery Summary ;
--------------------
No paths to report.


-------------------
; Removal Summary ;
-------------------
No paths to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Pulse Width                                                                                                                                                     ;
+--------+--------------+----------------+--------+---------+------------+------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Pulse  ; Clock   ; Clock Edge ; Target                                                                                         ;
+--------+--------------+----------------+--------+---------+------------+------------------------------------------------------------------------------------------------+
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[2]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[0]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[1]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[3]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[4]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[5]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[6]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|q_b[7]                          ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_we_reg       ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_re_reg       ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg0 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg1 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg2 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_address_reg3 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg0 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg4  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg1 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg2 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; rdclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~portb_address_reg3 ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg1  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg2  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg3  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg5  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg6  ;
; -4.555 ; 1.000        ; 5.555          ; Period ; wrclock ; Rise       ; altsyncram:altsyncram_component|altsyncram_0un1:auto_generated|ram_block1a0~porta_datain_reg7  ;
; -1.857 ; 1.000        ; 2.857          ; Period ; wrclock ; Rise       ; pw[0]                                                                                          ;
; -1.857 ; 1.000        ; 2.857          ; Period ; wrclock ; Rise       ; pw[1]                                                                                          ;
; -1.857 ; 1.000        ; 2.857          ; Period ; wrclock ; Rise       ; pw[2]                                                                                          ;
; -1.857 ; 1.000        ; 2.857          ; Period ; wrclock ; Rise       ; pw[3]                                                                                          ;
; -1.857 ; 1.000        ; 2.857          ; Period ; rdclock ; Rise       ; pr[0]                                                                                          ;
; -1.857 ; 1.000        ; 2.857          ; Period ; rdclock ; Rise       ; pr[1]                                                                                          ;