fifo.tan.rpt

TCC221图像传感器和FPGA实现图像采集

                Info: Total cell delay = 1.267 ns ( 55.28 % )
                Info: Total interconnect delay = 1.025 ns ( 44.72 % )
            Info: - Longest clock path from clock "rdclock" to source memory is 2.350 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'
                Info: 3: + IC(0.682 ns) + CELL(0.471 ns) = 2.350 ns; Loc. = M512_X36_Y3; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0'
                Info: Total cell delay = 1.325 ns ( 56.38 % )
                Info: Total interconnect delay = 1.025 ns ( 43.62 % )
        Info: + Micro clock to output delay of source is 0.140 ns
        Info: + Micro setup delay of destination is 0.022 ns
Info: Clock "wrclock" Internal fmax is restricted to 500.0 MHz between source memory "altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0" and destination memory "altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0"
    Info: fmax restricted to Clock High delay (1.0 ns) plus Clock Low delay (1.0 ns) : restricted to 2.0 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 1.720 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0'
            Info: 2: + IC(0.000 ns) + CELL(1.720 ns) = 1.720 ns; Loc. = M512_X36_Y3; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0'
            Info: Total cell delay = 1.720 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.046 ns
            Info: + Shortest clock path from clock "wrclock" to destination memory is 2.302 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'wrclock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 20; COMB Node = 'wrclock~clkctrl'
                Info: 3: + IC(0.682 ns) + CELL(0.413 ns) = 2.302 ns; Loc. = M512_X36_Y3; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0'
                Info: Total cell delay = 1.277 ns ( 55.47 % )
                Info: Total interconnect delay = 1.025 ns ( 44.53 % )
            Info: - Longest clock path from clock "wrclock" to source memory is 2.348 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'wrclock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 20; COMB Node = 'wrclock~clkctrl'
                Info: 3: + IC(0.682 ns) + CELL(0.459 ns) = 2.348 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0'
                Info: Total cell delay = 1.323 ns ( 56.35 % )
                Info: Total interconnect delay = 1.025 ns ( 43.65 % )
        Info: + Micro clock to output delay of source is 0.140 ns
        Info: + Micro setup delay of destination is 0.022 ns
Info: tsu for register "pr[2]" (data pin = "clr", clock pin = "rdclock") is 2.758 ns
    Info: + Longest pin to register delay is 5.165 ns
        Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U7; Fanout = 4; PIN Node = 'clr'
        Info: 2: + IC(3.815 ns) + CELL(0.378 ns) = 5.010 ns; Loc. = LCCOMB_X37_Y3_N14; Fanout = 1; COMB Node = 'pr[2]~150'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.165 ns; Loc. = LCFF_X37_Y3_N15; Fanout = 3; REG Node = 'pr[2]'
        Info: Total cell delay = 1.350 ns ( 26.14 % )
        Info: Total interconnect delay = 3.815 ns ( 73.86 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "rdclock" to destination register is 2.497 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'
        Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X37_Y3_N15; Fanout = 3; REG Node = 'pr[2]'
        Info: Total cell delay = 1.472 ns ( 58.95 % )
        Info: Total interconnect delay = 1.025 ns ( 41.05 % )
Info: tco from clock "rdclock" to destination pin "q[6]" through memory "altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6]" is 5.390 ns
    Info: + Longest clock path from clock "rdclock" to source memory is 2.292 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'
        Info: 3: + IC(0.682 ns) + CELL(0.413 ns) = 2.292 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6]'
        Info: Total cell delay = 1.267 ns ( 55.28 % )
        Info: Total interconnect delay = 1.025 ns ( 44.72 % )
    Info: + Micro clock to output delay of source is 0.140 ns
    Info: + Longest memory to pin delay is 2.958 ns
        Info: 1: + IC(0.000 ns) + CELL(0.065 ns) = 0.065 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6]'
        Info: 2: + IC(0.759 ns) + CELL(2.134 ns) = 2.958 ns; Loc. = PIN_U5; Fanout = 0; PIN Node = 'q[6]'
        Info: Total cell delay = 2.199 ns ( 74.34 % )
        Info: Total interconnect delay = 0.759 ns ( 25.66 % )
Info: th for memory "altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0" (data pin = "data[0]", clock pin = "wrclock") is -2.003 ns
    Info: + Longest clock path from clock "wrclock" to destination memory is 2.348 ns
        Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'wrclock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 20; COMB Node = 'wrclock~clkctrl'
        Info: 3: + IC(0.682 ns) + CELL(0.459 ns) = 2.348 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0'
        Info: Total cell delay = 1.323 ns ( 56.35 % )
        Info: Total interconnect delay = 1.025 ns ( 43.65 % )
    Info: + Micro hold delay of destination is 0.203 ns
    Info: - Shortest pin to memory delay is 4.554 ns
        Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_R8; Fanout = 1; PIN Node = 'data[0]'
        Info: 2: + IC(3.640 ns) + CELL(0.134 ns) = 4.554 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0'
        Info: Total cell delay = 0.914 ns ( 20.07 % )
        Info: Total interconnect delay = 3.640 ns ( 79.93 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 129 megabytes of memory during processing
    Info: Processing ended: Sat Jun 14 10:38:59 2008
    Info: Elapsed time: 00:00:03