fifo.tan.rpt

TCC221图像传感器和FPGA实现图像采集

+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                    ;
+-------+--------------+------------+---------+-----------------------------------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To                                                                                            ; To Clock ;
+-------+--------------+------------+---------+-----------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 2.758 ns   ; clr     ; pr[2]                                                                                         ; rdclock  ;
; N/A   ; None         ; 2.756 ns   ; clr     ; pr[3]                                                                                         ; rdclock  ;
; N/A   ; None         ; 2.634 ns   ; clr     ; pr[1]                                                                                         ; rdclock  ;
; N/A   ; None         ; 2.579 ns   ; data[2] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg2 ; wrclock  ;
; N/A   ; None         ; 2.563 ns   ; data[4] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg4 ; wrclock  ;
; N/A   ; None         ; 2.541 ns   ; data[1] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg1 ; wrclock  ;
; N/A   ; None         ; 2.537 ns   ; data[7] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg7 ; wrclock  ;
; N/A   ; None         ; 2.440 ns   ; data[3] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg3 ; wrclock  ;
; N/A   ; None         ; 2.398 ns   ; data[5] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg5 ; wrclock  ;
; N/A   ; None         ; 2.373 ns   ; clr     ; pr[0]                                                                                         ; rdclock  ;
; N/A   ; None         ; 2.286 ns   ; data[6] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg6 ; wrclock  ;
; N/A   ; None         ; 2.228 ns   ; data[0] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 ; wrclock  ;
+-------+--------------+------------+---------+-----------------------------------------------------------------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                           ;
+-------+--------------+------------+-----------------------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                  ; To   ; From Clock ;
+-------+--------------+------------+-----------------------------------------------------------------------+------+------------+
; N/A   ; None         ; 5.390 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] ; q[6] ; rdclock    ;
; N/A   ; None         ; 5.381 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[2] ; q[2] ; rdclock    ;
; N/A   ; None         ; 5.347 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[7] ; q[7] ; rdclock    ;
; N/A   ; None         ; 5.345 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[4] ; q[4] ; rdclock    ;
; N/A   ; None         ; 5.332 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[5] ; q[5] ; rdclock    ;
; N/A   ; None         ; 5.126 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[1] ; q[1] ; rdclock    ;
; N/A   ; None         ; 5.079 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[3] ; q[3] ; rdclock    ;
; N/A   ; None         ; 4.975 ns   ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] ; q[0] ; rdclock    ;
+-------+--------------+------------+-----------------------------------------------------------------------+------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                           ;
+---------------+-------------+-----------+---------+-----------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To                                                                                            ; To Clock ;
+---------------+-------------+-----------+---------+-----------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -2.003 ns ; data[0] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 ; wrclock  ;
; N/A           ; None        ; -2.061 ns ; data[6] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg6 ; wrclock  ;
; N/A           ; None        ; -2.134 ns ; clr     ; pr[0]                                                                                         ; rdclock  ;
; N/A           ; None        ; -2.173 ns ; data[5] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg5 ; wrclock  ;
; N/A           ; None        ; -2.215 ns ; data[3] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg3 ; wrclock  ;
; N/A           ; None        ; -2.312 ns ; data[7] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg7 ; wrclock  ;
; N/A           ; None        ; -2.316 ns ; data[1] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg1 ; wrclock  ;
; N/A           ; None        ; -2.338 ns ; data[4] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg4 ; wrclock  ;
; N/A           ; None        ; -2.354 ns ; data[2] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg2 ; wrclock  ;
; N/A           ; None        ; -2.395 ns ; clr     ; pr[1]                                                                                         ; rdclock  ;
; N/A           ; None        ; -2.517 ns ; clr     ; pr[3]                                                                                         ; rdclock  ;
; N/A           ; None        ; -2.519 ns ; clr     ; pr[2]                                                                                         ; rdclock  ;
+---------------+-------------+-----------+---------+-----------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Jun 14 10:38:56 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fifo -c fifo --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "rdclock" is an undefined clock
    Info: Assuming node "wrclock" is an undefined clock
Info: Clock "rdclock" Internal fmax is restricted to 500.0 MHz between source memory "altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0" and destination memory "altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0]"
    Info: fmax restricted to Clock High delay (1.0 ns) plus Clock Low delay (1.0 ns) : restricted to 2.0 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 1.720 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X36_Y3; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0'
            Info: 2: + IC(0.000 ns) + CELL(1.720 ns) = 1.720 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0]'
            Info: Total cell delay = 1.720 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.058 ns
            Info: + Shortest clock path from clock "rdclock" to destination memory is 2.292 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'
                Info: 3: + IC(0.682 ns) + CELL(0.413 ns) = 2.292 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0]'