📄 fifo.tan.rpt
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; rdclock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; wrclock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'rdclock' ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[1] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[1] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[1] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[1] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[2] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[2] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[2] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[2] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[3] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[3] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[3] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[3] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[4] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[4] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[4] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[4] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[5] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[5] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[5] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[5] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[7] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[7] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[7] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[7] ; rdclock ; rdclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[3] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg3 ; rdclock ; rdclock ; None ; None ; 0.809 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[0] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 ; rdclock ; rdclock ; None ; None ; 0.733 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[1] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg1 ; rdclock ; rdclock ; None ; None ; 0.725 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[2] ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg2 ; rdclock ; rdclock ; None ; None ; 0.715 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[0] ; pr[3] ; rdclock ; rdclock ; None ; None ; 0.687 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[1] ; pr[3] ; rdclock ; rdclock ; None ; None ; 0.684 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[1] ; pr[2] ; rdclock ; rdclock ; None ; None ; 0.681 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[0] ; pr[1] ; rdclock ; rdclock ; None ; None ; 0.438 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[0] ; pr[2] ; rdclock ; rdclock ; None ; None ; 0.434 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[2] ; pr[3] ; rdclock ; rdclock ; None ; None ; 0.417 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[0] ; pr[0] ; rdclock ; rdclock ; None ; None ; 0.396 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[1] ; pr[1] ; rdclock ; rdclock ; None ; None ; 0.396 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[2] ; pr[2] ; rdclock ; rdclock ; None ; None ; 0.396 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pr[3] ; pr[3] ; rdclock ; rdclock ; None ; None ; 0.396 ns ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'wrclock' ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg1 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a1~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg2 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a2~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg3 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a3~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg4 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a4~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg5 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a5~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg6 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a6~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg7 ; altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a7~porta_memory_reg0 ; wrclock ; wrclock ; None ; None ; 1.720 ns ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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