test_div.map.rpt

Altera的FPGA设计的硬件除法器

; Parameter Settings for User Entity Instance: divide0:inst|lpm_divide:lpm_divide_component ;
+------------------------+----------------+-------------------------------------------------+
; Parameter Name         ; Value          ; Type                                            ;
+------------------------+----------------+-------------------------------------------------+
; LPM_WIDTHN             ; 16             ; Integer                                         ;
; LPM_WIDTHD             ; 16             ; Integer                                         ;
; LPM_NREPRESENTATION    ; SIGNED         ; Untyped                                         ;
; LPM_DREPRESENTATION    ; SIGNED         ; Untyped                                         ;
; LPM_PIPELINE           ; 0              ; Untyped                                         ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                         ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                         ;
; CBXI_PARAMETER         ; lpm_divide_q8p ; Untyped                                         ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                         ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                         ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                      ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                    ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                    ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                  ;
+------------------------+----------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jun 19 11:06:03 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test_div -c test_div
Info: Found 1 design units, including 1 entities, in source file test_div.bdf
    Info: Found entity 1: test_div
Info: Elaborating entity "test_div" for the top level hierarchy
Warning: Using design file divide0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: divide0-SYN
    Info: Found entity 1: divide0
Info: Elaborating entity "divide0" for hierarchy "divide0:inst"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborating entity "lpm_divide" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component"
Info: Elaborated megafunction instantiation "divide0:inst|lpm_divide:lpm_divide_component"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_q8p.tdf
    Info: Found entity 1: lpm_divide_q8p
Info: Elaborating entity "lpm_divide_q8p" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_79h.tdf
    Info: Found entity 1: sign_div_unsign_79h
Info: Elaborating entity "sign_div_unsign_79h" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider"
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_aue.tdf
    Info: Found entity 1: alt_u_div_aue
Info: Elaborating entity "alt_u_div_aue" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf
    Info: Found entity 1: add_sub_3dc
Info: Elaborating entity "add_sub_3dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_3dc:add_sub_0"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf
    Info: Found entity 1: add_sub_4dc
Info: Elaborating entity "add_sub_4dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_4dc:add_sub_1"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_kec.tdf
    Info: Found entity 1: add_sub_kec
Info: Elaborating entity "add_sub_kec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_kec:add_sub_10"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lec.tdf
    Info: Found entity 1: add_sub_lec
Info: Elaborating entity "add_sub_lec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_lec:add_sub_11"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mec.tdf
    Info: Found entity 1: add_sub_mec
Info: Elaborating entity "add_sub_mec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_mec:add_sub_12"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_nec.tdf
    Info: Found entity 1: add_sub_nec
Info: Elaborating entity "add_sub_nec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_nec:add_sub_13"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_oec.tdf
    Info: Found entity 1: add_sub_oec
Info: Elaborating entity "add_sub_oec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_oec:add_sub_14"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_pec.tdf
    Info: Found entity 1: add_sub_pec
Info: Elaborating entity "add_sub_pec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_pec:add_sub_15"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf
    Info: Found entity 1: add_sub_5dc
Info: Elaborating entity "add_sub_5dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_5dc:add_sub_2"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf
    Info: Found entity 1: add_sub_6dc
Info: Elaborating entity "add_sub_6dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_6dc:add_sub_3"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf
    Info: Found entity 1: add_sub_7dc
Info: Elaborating entity "add_sub_7dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_7dc:add_sub_4"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_8dc.tdf
    Info: Found entity 1: add_sub_8dc
Info: Elaborating entity "add_sub_8dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_8dc:add_sub_5"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_9dc.tdf
    Info: Found entity 1: add_sub_9dc
Info: Elaborating entity "add_sub_9dc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_9dc:add_sub_6"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_adc.tdf
    Info: Found entity 1: add_sub_adc
Info: Elaborating entity "add_sub_adc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_adc:add_sub_7"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_bdc.tdf
    Info: Found entity 1: add_sub_bdc
Info: Elaborating entity "add_sub_bdc" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_bdc:add_sub_8"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_jec.tdf
    Info: Found entity 1: add_sub_jec
Info: Elaborating entity "add_sub_jec" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|alt_u_div_aue:divider|add_sub_jec:add_sub_9"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_oac.tdf
    Info: Found entity 1: add_sub_oac
Info: Elaborating entity "add_sub_oac" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|add_sub_oac:adder"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_g6f.tdf
    Info: Found entity 1: add_sub_g6f
Info: Elaborating entity "add_sub_g6f" for hierarchy "divide0:inst|lpm_divide:lpm_divide_component|lpm_divide_q8p:auto_generated|sign_div_unsign_79h:divider|add_sub_g6f:compl_adder1"
Info: Ignored 62 buffer(s)
    Info: Ignored 62 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "QUOTIENT[16]" stuck at GND
Info: Implemented 479 device resources after synthesis - the final resource count might be different
    Info: Implemented 32 input pins
    Info: Implemented 33 output pins
    Info: Implemented 414 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu Jun 19 11:06:10 2008
    Info: Elapsed time: 00:00:08