alt_u_div_bqe.tdf

Altera的FPGA设计的硬件除法器

RETURNS ( cout, result[8..0]);
FUNCTION add_sub_gac (dataa[9..0], datab[9..0])
RETURNS ( cout, result[9..0]);

--synthesis_resources = lut 133 
SUBDESIGN alt_u_div_bqe
( 
	den_out[15..0]	:	output;
	denominator[15..0]	:	input;
	numerator[15..0]	:	input;
	quotient[15..0]	:	output;
	remainder[15..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_09c;
	add_sub_1 : add_sub_19c;
	add_sub_10 : add_sub_hac;
	add_sub_11 : add_sub_iac;
	add_sub_12 : add_sub_jac;
	add_sub_13 : add_sub_kac;
	add_sub_14 : add_sub_lac;
	add_sub_15 : add_sub_nac;
	add_sub_2 : add_sub_29c;
	add_sub_3 : add_sub_39c;
	add_sub_4 : add_sub_49c;
	add_sub_5 : add_sub_59c;
	add_sub_6 : add_sub_69c;
	add_sub_7 : add_sub_79c;
	add_sub_8 : add_sub_89c;
	add_sub_9 : add_sub_gac;
	DenominatorIn[288..0]	: WIRE;
	DenominatorIn_tmp[288..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[271..0]	: WIRE;
	NumeratorIn[271..0]	: WIRE;
	NumeratorIn_tmp[271..0]	: WIRE;
	prestg[255..0]	: WIRE;
	quotient_tmp[15..0]	: WIRE;
	sel[271..0]	: WIRE;
	selnose[271..0]	: WIRE;
	StageIn[271..0]	: WIRE;
	StageIn_tmp[271..0]	: WIRE;
	StageOut[255..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[15..15];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[16..16], NumeratorIn[30..30]);