sign_div_unsign_39h.tdf

Altera的FPGA设计的硬件除法器

--sign_div_unsign DEN_REPRESENTATION="SIGNED" DEN_WIDTH=32 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" NUM_WIDTH=32 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_abs 2006:01:02:19:20:00:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION alt_u_div_2ue (denominator[31..0], numerator[31..0])
RETURNS ( den_out[31..0], quotient[31..0], remainder[31..0]);
FUNCTION add_sub_mac (cin, dataa[31..0], datab[31..0])
RETURNS ( result[31..0]);
FUNCTION add_sub_e6f (cin, dataa[31..0], datab[31..0])
RETURNS ( result[31..0]);

--synthesis_resources = lut 591 
SUBDESIGN sign_div_unsign_39h
( 
	denominator[31..0]	:	input;
	numerator[31..0]	:	input;
	quotient[31..0]	:	output;
	remainder[31..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_2ue;
	adder : add_sub_mac;
	compl_adder1 : add_sub_e6f;
	compl_adder_4 : add_sub_e6f;
	adder_out[31..0]	: WIRE;
	den_choice[31..0]	: WIRE;
	gnd_wire	: WIRE;
	neg_num[31..0]	: WIRE;
	neg_quot[31..0]	: WIRE;
	norm_num[31..0]	: WIRE;
	num_choice[31..0]	: WIRE;
	pre_neg_den[31..0]	: WIRE;
	pre_neg_quot[31..0]	: WIRE;
	pre_quot[31..0]	: WIRE;
	protect_quotient[31..0]	: WIRE;
	protect_remainder[31..0]	: WIRE;
	q_is_neg	: WIRE;
	vcc_wire	: WIRE;
	zero_wire[31..0]	: WIRE;
	zero_wire_3[31..0]	: WIRE;

BEGIN 
	divider.denominator[] = den_choice[];
	divider.numerator[] = norm_num[];
	adder.cin = gnd_wire;
	adder.dataa[] = den_choice[];
	adder.datab[] = protect_remainder[];
	compl_adder1.cin = vcc_wire;
	compl_adder1.dataa[] = (! denominator[]);
	compl_adder1.datab[] = zero_wire[];
	compl_adder_4.cin = vcc_wire;
	compl_adder_4.dataa[] = (! pre_quot[]);
	compl_adder_4.datab[] = zero_wire_3[];
	adder_out[] = adder.result[];
	den_choice[] = ((denominator[] & (! denominator[31..31])) # (pre_neg_den[] & denominator[31..31]));
	gnd_wire = B"0";
	neg_num[] = (! num_choice[]);
	neg_quot[] = (! protect_quotient[]);
	norm_num[] = ((num_choice[] & (! num_choice[31..31])) # (neg_num[] & num_choice[31..31]));
	num_choice[] = numerator[];
	pre_neg_den[] = compl_adder1.result[];
	pre_neg_quot[] = compl_adder_4.result[];
	pre_quot[] = ((protect_quotient[] & (! num_choice[31..31])) # (neg_quot[] & num_choice[31..31]));
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	q_is_neg = denominator[31..31];
	quotient[] = ((pre_quot[] & (! q_is_neg)) # (pre_neg_quot[] & q_is_neg));
	remainder[] = ((protect_remainder[] & (! num_choice[31..31])) # (adder_out[] & num_choice[31..31]));
	vcc_wire = B"1";
	zero_wire[] = B"00000000000000000000000000000000";
	zero_wire_3[] = B"00000000000000000000000000000000";
END;
--VALID FILE