lpm_divide_r4p.tdf

Altera的FPGA设计的硬件除法器

--lpm_divide DEVICE_FAMILY="MAX3000A" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="TRUE" LPM_WIDTHD=16 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=9 denom numer quotient remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_abs 2006:01:02:19:20:00:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION sign_div_unsign_b9h (denominator[15..0], numerator[15..0])
RETURNS ( quotient[15..0], remainder[15..0]);

--synthesis_resources = lut 167 
SUBDESIGN lpm_divide_r4p
( 
	denom[15..0]	:	input;
	numer[15..0]	:	input;
	quotient[15..0]	:	output;
	remain[15..0]	:	output;
) 
VARIABLE 
	divider : sign_div_unsign_b9h;
	numer_tmp[15..0]	: WIRE;

BEGIN 
	divider.denominator[] = denom[];
	divider.numerator[] = numer_tmp[];
	numer_tmp[] = numer[];
	quotient[] = divider.quotient[];
	remain[] = divider.remainder[];
END;
--VALID FILE