test_div.fit.summary

来自「Altera的FPGA设计的硬件除法器」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Thu Jun 19 11:06:20 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : test_div
Top-level Entity Name : test_div
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 414 / 2,910 ( 14 % )
Total pins : 65 / 104 ( 63 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )