test_div.map.summary

Altera的FPGA设计的硬件除法器

Analysis & Synthesis Status : Successful - Thu Jun 19 11:06:10 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : test_div
Top-level Entity Name : test_div
Family : Cyclone
Total logic elements : 414
Total pins : 65
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0