ddr_6to1_16chan_rt_tx.vhd

FPGA之间的LVDS传输

   

   OSERDES_TX_DATA_08 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(08),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(048),
         D2 => DATA_TO_OSERDES_REG(049),
         D3 => DATA_TO_OSERDES_REG(050),
         D4 => DATA_TO_OSERDES_REG(051),
         D5 => DATA_TO_OSERDES_REG(052),
         D6 => DATA_TO_OSERDES_REG(053),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_09 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)

      PORT MAP (
         OQ => TX_DATA_PREBUF(09),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(054),
         D2 => DATA_TO_OSERDES_REG(055),
         D3 => DATA_TO_OSERDES_REG(056),
         D4 => DATA_TO_OSERDES_REG(057),
         D5 => DATA_TO_OSERDES_REG(058),
         D6 => DATA_TO_OSERDES_REG(059),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_10 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(10),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(060),
         D2 => DATA_TO_OSERDES_REG(061),
         D3 => DATA_TO_OSERDES_REG(062),
         D4 => DATA_TO_OSERDES_REG(063),
         D5 => DATA_TO_OSERDES_REG(064),
         D6 => DATA_TO_OSERDES_REG(065),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   
   
   OSERDES_TX_DATA_11 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(11),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(066),
         D2 => DATA_TO_OSERDES_REG(067),
         D3 => DATA_TO_OSERDES_REG(068),
         D4 => DATA_TO_OSERDES_REG(069),
         D5 => DATA_TO_OSERDES_REG(070),
         D6 => DATA_TO_OSERDES_REG(071),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_12 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(12),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(072),
         D2 => DATA_TO_OSERDES_REG(073),
         D3 => DATA_TO_OSERDES_REG(074),
         D4 => DATA_TO_OSERDES_REG(075),
         D5 => DATA_TO_OSERDES_REG(076),
         D6 => DATA_TO_OSERDES_REG(077),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_13 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(13),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(078),
         D2 => DATA_TO_OSERDES_REG(079),
         D3 => DATA_TO_OSERDES_REG(080),
         D4 => DATA_TO_OSERDES_REG(081),
         D5 => DATA_TO_OSERDES_REG(082),
         D6 => DATA_TO_OSERDES_REG(083),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_14 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)

      PORT MAP (
         OQ => TX_DATA_PREBUF(14),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(084),
         D2 => DATA_TO_OSERDES_REG(085),
         D3 => DATA_TO_OSERDES_REG(086),
         D4 => DATA_TO_OSERDES_REG(087),
         D5 => DATA_TO_OSERDES_REG(088),
         D6 => DATA_TO_OSERDES_REG(089),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_15 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 6, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(15),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(090),
         D2 => DATA_TO_OSERDES_REG(091),
         D3 => DATA_TO_OSERDES_REG(092),
         D4 => DATA_TO_OSERDES_REG(093),
         D5 => DATA_TO_OSERDES_REG(094),
         D6 => DATA_TO_OSERDES_REG(095),
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   
   
   --SLAVE OSERDES IN DATA PATH
  	
	--OUTPUT BUFFERS	

   OBUFDS_TX_DATA_00 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(00),
         OB => DATA_TX_N(00),
         I => TX_DATA_PREBUF(00));   
   

   OBUFDS_TX_DATA_01 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(01),
         OB => DATA_TX_N(01),
         I => TX_DATA_PREBUF(01));   
   

   OBUFDS_TX_DATA_02 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(02),
         OB => DATA_TX_N(02),
         I => TX_DATA_PREBUF(02));   
   

   OBUFDS_TX_DATA_03 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(03),
         OB => DATA_TX_N(03),
         I => TX_DATA_PREBUF(03));   
   

   OBUFDS_TX_DATA_04 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(04),
         OB => DATA_TX_N(04),
         I => TX_DATA_PREBUF(04));   
   

   OBUFDS_TX_DATA_05 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(05),
         OB => DATA_TX_N(05),
         I => TX_DATA_PREBUF(05));   
   

   OBUFDS_TX_DATA_06 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(06),
         OB => DATA_TX_N(06),
         I => TX_DATA_PREBUF(06));   
   

   OBUFDS_TX_DATA_07 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(07),
         OB => DATA_TX_N(07),
         I => TX_DATA_PREBUF(07));   
   

   OBUFDS_TX_DATA_08 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(08),
         OB => DATA_TX_N(08),
         I => TX_DATA_PREBUF(08));   
   

   OBUFDS_TX_DATA_09 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(09),
         OB => DATA_TX_N(09),
         I => TX_DATA_PREBUF(09));   
   

   OBUFDS_TX_DATA_10 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(10),
         OB => DATA_TX_N(10),
         I => TX_DATA_PREBUF(10));   
   

   OBUFDS_TX_DATA_11 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(11),
         OB => DATA_TX_N(11),
         I => TX_DATA_PREBUF(11));   
   

   OBUFDS_TX_DATA_12 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(12),
         OB => DATA_TX_N(12),
         I => TX_DATA_PREBUF(12));   
   

   OBUFDS_TX_DATA_13 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(13),
         OB => DATA_TX_N(13),
         I => TX_DATA_PREBUF(13));   
   

   OBUFDS_TX_DATA_14 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(14),
         OB => DATA_TX_N(14),
         I => TX_DATA_PREBUF(14));   
   

   OBUFDS_TX_DATA_15 : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => DATA_TX_P(15),
         OB => DATA_TX_N(15),
         I => TX_DATA_PREBUF(15));   
   

END translated;