📄 ddr_6to1_16chan_rt_tx.vhd
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--/////////////////////////////////////////////////////////////////////////////
--
-- File Name: DDR_6TO1_16CHAN_RT_TX.vhd
-- Version: 1.0
-- Date: 08/07/06
-- Model: XAPP860 LVDS Transmitter Module
--
-- Company: Xilinx, Inc.
-- Contributor: APD Applications Group
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2006 Xilinx, Inc.
-- All rights reserved.
--
--/////////////////////////////////////////////////////////////////////////////
--
-- Summary:
--
-- The DDR_6TO1_16CHAN_RT_TX module contains all components in the XAPP860 LVDS Transmitter,
-- including 16 channels of LVDS data, one channel of LVDS clock, and a multiplexer
-- that selects between a training pattern and user data.
--
------------------------------------------------------------------
----
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
ENTITY DDR_6TO1_16CHAN_RT_TX IS
PORT (
DATA_TX_P : OUT std_logic_vector(15 DOWNTO 0); -- SERIAL SIDE TX DATA (P)
DATA_TX_N : OUT std_logic_vector(15 DOWNTO 0); -- SERIAL SIDE TX DATA (N)
CLOCK_TX_P : OUT std_logic; -- FORWARDED CLOCK TO RX (P)
CLOCK_TX_N : OUT std_logic; -- FORWARDED CLOCK TO RX (N)
TXCLK : IN std_logic; -- SERIAL SIDE TX CLOCK
TXCLKDIV : IN std_logic; -- PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
DATA_TO_OSERDES : IN std_logic_vector(95 DOWNTO 0); -- PARALLEL SIDE TX DATA
RESET : IN std_logic; -- TX DOMAIN RESET
TRAINING_DONE : IN std_logic); -- FLAG FROM RECEIVER INDICATING ALIGNMENT
END DDR_6TO1_16CHAN_RT_TX;
ARCHITECTURE translated OF DDR_6TO1_16CHAN_RT_TX IS
SIGNAL TX_CLOCK_PREBUF : std_logic;
SIGNAL TX_DATA_PREBUF : std_logic_vector(15 DOWNTO 0);
SIGNAL DATA_TO_OSERDES_REG : std_logic_vector(95 DOWNTO 0);
BEGIN
--DATA SOURCE: TRAINING PAT OR PRBS
--IF NO FEEDBACK CONTROLS FROM RX ARE DESIRED, THE TX CAN BE SET TO SEND THE
--TRAINING PATTERN FOR A FIXED AMOUNT OF TIME, AFTER WHICH IT AUTOMATICALLY
--ASSUMES THAT TRAINING IS COMPLETE AND BEGINS SENDING USER DATA.
PROCESS (TXCLKDIV)
BEGIN
IF (TXCLKDIV'EVENT AND TXCLKDIV = '1') THEN
IF (TRAINING_DONE = '1') THEN
DATA_TO_OSERDES_REG <= DATA_TO_OSERDES; -- PRBS
ELSE
DATA_TO_OSERDES_REG <= "101100101100101100101100101100101100101100101100101100101100101100101100101100101100101100101100"; -- TRAINING PATTERN = 101100
END IF;
END IF;
END PROCESS;
--FORWARDED CLOCK
ODDR_TX_CLOCK : ODDR
GENERIC MAP(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0', SRTYPE => "ASYNC")
PORT MAP (
Q => TX_CLOCK_PREBUF,
C => TXCLK,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
--FORWARDED CLOCK OUTPUT BUFFER
OBUFDS_TX_CLOCK : OBUFDS_LVDSEXT_25
PORT MAP (
O => CLOCK_TX_P,
OB => CLOCK_TX_N,
I => TX_CLOCK_PREBUF);
--MASTER OSERDES IN DATA PATH
OSERDES_TX_DATA_00 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(00),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(000),
D2 => DATA_TO_OSERDES_REG(001),
D3 => DATA_TO_OSERDES_REG(002),
D4 => DATA_TO_OSERDES_REG(003),
D5 => DATA_TO_OSERDES_REG(004),
D6 => DATA_TO_OSERDES_REG(005),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_01 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(01),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(006),
D2 => DATA_TO_OSERDES_REG(007),
D3 => DATA_TO_OSERDES_REG(008),
D4 => DATA_TO_OSERDES_REG(009),
D5 => DATA_TO_OSERDES_REG(010),
D6 => DATA_TO_OSERDES_REG(011),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_02 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(02),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(012),
D2 => DATA_TO_OSERDES_REG(013),
D3 => DATA_TO_OSERDES_REG(014),
D4 => DATA_TO_OSERDES_REG(015),
D5 => DATA_TO_OSERDES_REG(016),
D6 => DATA_TO_OSERDES_REG(017),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_03 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(03),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(018),
D2 => DATA_TO_OSERDES_REG(019),
D3 => DATA_TO_OSERDES_REG(020),
D4 => DATA_TO_OSERDES_REG(021),
D5 => DATA_TO_OSERDES_REG(022),
D6 => DATA_TO_OSERDES_REG(023),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_04 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(04),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(024),
D2 => DATA_TO_OSERDES_REG(025),
D3 => DATA_TO_OSERDES_REG(026),
D4 => DATA_TO_OSERDES_REG(027),
D5 => DATA_TO_OSERDES_REG(028),
D6 => DATA_TO_OSERDES_REG(029),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_05 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(05),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(030),
D2 => DATA_TO_OSERDES_REG(031),
D3 => DATA_TO_OSERDES_REG(032),
D4 => DATA_TO_OSERDES_REG(033),
D5 => DATA_TO_OSERDES_REG(034),
D6 => DATA_TO_OSERDES_REG(035),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_06 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(06),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(036),
D2 => DATA_TO_OSERDES_REG(037),
D3 => DATA_TO_OSERDES_REG(038),
D4 => DATA_TO_OSERDES_REG(039),
D5 => DATA_TO_OSERDES_REG(040),
D6 => DATA_TO_OSERDES_REG(041),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
OSERDES_TX_DATA_07 : OSERDES
GENERIC MAP(
DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR", DATA_WIDTH => 6,
INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER",
SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
PORT MAP (
OQ => TX_DATA_PREBUF(07),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => TXCLK,
CLKDIV => TXCLKDIV,
D1 => DATA_TO_OSERDES_REG(042),
D2 => DATA_TO_OSERDES_REG(043),
D3 => DATA_TO_OSERDES_REG(044),
D4 => DATA_TO_OSERDES_REG(045),
D5 => DATA_TO_OSERDES_REG(046),
D6 => DATA_TO_OSERDES_REG(047),
OCE => '1',
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => RESET,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '0');
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