📄 ddr_6to1_16chan_rt_rx.vhd
字号:
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(10),
IDATAIN => DATA_RX_BUF(10),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_10,
INC => RX_DATA_INC_10,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_11 <= ICE_DELAY OR ICE_TO_ISERDES(11) OR ICE_TO_ISERDES_RT(11);
RX_DATA_INC_11 <= INC_DELAY OR INC_TO_ISERDES(11) OR INC_TO_ISERDES_RT(11);
IODELAY_RX_DATA_11 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(11),
IDATAIN => DATA_RX_BUF(11),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_11,
INC => RX_DATA_INC_11,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_12 <= ICE_DELAY OR ICE_TO_ISERDES(12) OR ICE_TO_ISERDES_RT(12);
RX_DATA_INC_12 <= INC_DELAY OR INC_TO_ISERDES(12) OR INC_TO_ISERDES_RT(12);
IODELAY_RX_DATA_12 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(12),
IDATAIN => DATA_RX_BUF(12),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_12,
INC => RX_DATA_INC_12,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_13 <= ICE_DELAY OR ICE_TO_ISERDES(13) OR ICE_TO_ISERDES_RT(13);
RX_DATA_INC_13 <= INC_DELAY OR INC_TO_ISERDES(13) OR INC_TO_ISERDES_RT(13);
IODELAY_RX_DATA_13 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(13),
IDATAIN => DATA_RX_BUF(13),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_13,
INC => RX_DATA_INC_13,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_14 <= ICE_DELAY OR ICE_TO_ISERDES(14) OR ICE_TO_ISERDES_RT(14);
RX_DATA_INC_14 <= INC_DELAY OR INC_TO_ISERDES(14) OR INC_TO_ISERDES_RT(14);
IODELAY_RX_DATA_14 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(14),
IDATAIN => DATA_RX_BUF(14),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_14,
INC => RX_DATA_INC_14,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_15 <= ICE_DELAY OR ICE_TO_ISERDES(15) OR ICE_TO_ISERDES_RT(15);
RX_DATA_INC_15 <= INC_DELAY OR INC_TO_ISERDES(15) OR INC_TO_ISERDES_RT(15);
IODELAY_RX_DATA_15 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(15),
IDATAIN => DATA_RX_BUF(15),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_15,
INC => RX_DATA_INC_15,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
--MASTER SIDE ISERDES
BITSLIP_00 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(00);
ISERDES_RX_DATA_00 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(005),
Q2 => DATA_FROM_ISERDES_TEMP(004),
Q3 => DATA_FROM_ISERDES_TEMP(003),
Q4 => DATA_FROM_ISERDES_TEMP(002),
Q5 => DATA_FROM_ISERDES_TEMP(001),
Q6 => DATA_FROM_ISERDES_TEMP(000),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_00,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(00),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_01 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(01);
ISERDES_RX_DATA_01 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(011),
Q2 => DATA_FROM_ISERDES_TEMP(010),
Q3 => DATA_FROM_ISERDES_TEMP(009),
Q4 => DATA_FROM_ISERDES_TEMP(008),
Q5 => DATA_FROM_ISERDES_TEMP(007),
Q6 => DATA_FROM_ISERDES_TEMP(006),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_01,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(01),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_02 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(02);
ISERDES_RX_DATA_02 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(017),
Q2 => DATA_FROM_ISERDES_TEMP(016),
Q3 => DATA_FROM_ISERDES_TEMP(015),
Q4 => DATA_FROM_ISERDES_TEMP(014),
Q5 => DATA_FROM_ISERDES_TEMP(013),
Q6 => DATA_FROM_ISERDES_TEMP(012),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_02,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(02),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_03 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(03);
ISERDES_RX_DATA_03 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(023),
Q2 => DATA_FROM_ISERDES_TEMP(022),
Q3 => DATA_FROM_ISERDES_TEMP(021),
Q4 => DATA_FROM_ISERDES_TEMP(020),
Q5 => DATA_FROM_ISERDES_TEMP(019),
Q6 => DATA_FROM_ISERDES_TEMP(018),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_03,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(03),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_04 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(04);
ISERDES_RX_DATA_04 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(029),
Q2 => DATA_FROM_ISERDES_TEMP(028),
Q3 => DATA_FROM_ISERDES_TEMP(027),
Q4 => DATA_FROM_ISERDES_TEMP(026),
Q5 => DATA_FROM_ISERDES_TEMP(025),
Q6 => DATA_FROM_ISERDES_TEMP(024),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_04,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(04),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_05 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(05);
ISERDES_RX_DATA_05 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(035),
Q2 => DATA_FROM_ISERDES_TEMP(034),
Q3 => DATA_FROM_ISERDES_TEMP(033),
Q4 => DATA_FROM_ISERDES_TEMP(032),
Q5 => DATA_FROM_ISERDES_TEMP(031),
Q6 => DATA_FROM_ISERDES_TEMP(030),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_05,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(05),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_06 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(06);
ISERDES_RX_DATA_06 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(041),
Q2 => DATA_FROM_ISERDES_TEMP(040),
Q3 => DATA_FROM_ISERDES_TEMP(039),
Q4 => DATA_FROM_ISERDES_TEMP(038),
Q5 => DATA_FROM_ISERDES_TEMP(037),
Q6 => DATA_FROM_ISERDES_TEMP(036),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => BITSLIP_06,
CE1 => '1',
CE2 => '0',
CLK => RXCLK_TEMP,
CLKB => NOT RXCLK_TEMP,
CLKDIV => RXCLKDIV_TEMP,
D => DATA_RX_IDLY(06),
OCLK => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => RESET);
BITSLIP_07 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(07);
ISERDES_RX_DATA_07 : ISERDES_NODELAY
GENERIC MAP(
BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 6,
INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
PORT MAP (
Q1 => DATA_FROM_ISERDES_TEMP(047),
Q2 => DATA_FROM_ISERDES_TEMP(046),
Q3 => DATA_FROM_ISERDES_TEMP(045),
Q4 => DATA_FROM_ISERDES_TEMP(044),
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