📄 ddr_6to1_16chan_rt_rx.vhd
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GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(07),
OB => DATA_RX_BUF_MON(07),
I => DATA_RX_P(07),
IB => DATA_RX_N(07));
RX_DATA_IN_08 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(08),
OB => DATA_RX_BUF_MON(08),
I => DATA_RX_P(08),
IB => DATA_RX_N(08));
RX_DATA_IN_09 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(09),
OB => DATA_RX_BUF_MON(09),
I => DATA_RX_P(09),
IB => DATA_RX_N(09));
RX_DATA_IN_10 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(10),
OB => DATA_RX_BUF_MON(10),
I => DATA_RX_P(10),
IB => DATA_RX_N(10));
RX_DATA_IN_11 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(11),
OB => DATA_RX_BUF_MON(11),
I => DATA_RX_P(11),
IB => DATA_RX_N(11));
RX_DATA_IN_12 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(12),
OB => DATA_RX_BUF_MON(12),
I => DATA_RX_P(12),
IB => DATA_RX_N(12));
RX_DATA_IN_13 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(13),
OB => DATA_RX_BUF_MON(13),
I => DATA_RX_P(13),
IB => DATA_RX_N(13));
RX_DATA_IN_14 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(14),
OB => DATA_RX_BUF_MON(14),
I => DATA_RX_P(14),
IB => DATA_RX_N(14));
RX_DATA_IN_15 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(15),
OB => DATA_RX_BUF_MON(15),
I => DATA_RX_P(15),
IB => DATA_RX_N(15));
--MASTER SIDE IODELAYS
RX_DATA_CE_00 <= ICE_DELAY OR ICE_TO_ISERDES(00) OR ICE_TO_ISERDES_RT(00);
RX_DATA_INC_00 <= INC_DELAY OR INC_TO_ISERDES(00) OR INC_TO_ISERDES_RT(00);
RX_DATA_RESET <= IDLY_RESET OR RESET;
IODELAY_RX_DATA_00 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(00),
IDATAIN => DATA_RX_BUF(00),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_00,
INC => RX_DATA_INC_00,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_01 <= ICE_DELAY OR ICE_TO_ISERDES(01) OR ICE_TO_ISERDES_RT(01);
RX_DATA_INC_01 <= INC_DELAY OR INC_TO_ISERDES(01) OR INC_TO_ISERDES_RT(01);
IODELAY_RX_DATA_01 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(01),
IDATAIN => DATA_RX_BUF(01),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_01,
INC => RX_DATA_INC_01,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_02 <= ICE_DELAY OR ICE_TO_ISERDES(02) OR ICE_TO_ISERDES_RT(02);
RX_DATA_INC_02 <= INC_DELAY OR INC_TO_ISERDES(02) OR INC_TO_ISERDES_RT(02);
IODELAY_RX_DATA_02 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(02),
IDATAIN => DATA_RX_BUF(02),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_02,
INC => RX_DATA_INC_02,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_03 <= ICE_DELAY OR ICE_TO_ISERDES(03) OR ICE_TO_ISERDES_RT(03);
RX_DATA_INC_03 <= INC_DELAY OR INC_TO_ISERDES(03) OR INC_TO_ISERDES_RT(03);
IODELAY_RX_DATA_03 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(03),
IDATAIN => DATA_RX_BUF(03),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_03,
INC => RX_DATA_INC_03,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_04 <= ICE_DELAY OR ICE_TO_ISERDES(04) OR ICE_TO_ISERDES_RT(04);
RX_DATA_INC_04 <= INC_DELAY OR INC_TO_ISERDES(04) OR INC_TO_ISERDES_RT(04);
IODELAY_RX_DATA_04 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(04),
IDATAIN => DATA_RX_BUF(04),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_04,
INC => RX_DATA_INC_04,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_05 <= ICE_DELAY OR ICE_TO_ISERDES(05) OR ICE_TO_ISERDES_RT(05);
RX_DATA_INC_05 <= INC_DELAY OR INC_TO_ISERDES(05) OR INC_TO_ISERDES_RT(05);
IODELAY_RX_DATA_05 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(05),
IDATAIN => DATA_RX_BUF(05),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_05,
INC => RX_DATA_INC_05,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_06 <= ICE_DELAY OR ICE_TO_ISERDES(06) OR ICE_TO_ISERDES_RT(06);
RX_DATA_INC_06 <= INC_DELAY OR INC_TO_ISERDES(06) OR INC_TO_ISERDES_RT(06);
IODELAY_RX_DATA_06 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(06),
IDATAIN => DATA_RX_BUF(06),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_06,
INC => RX_DATA_INC_06,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_07 <= ICE_DELAY OR ICE_TO_ISERDES(07) OR ICE_TO_ISERDES_RT(07);
RX_DATA_INC_07 <= INC_DELAY OR INC_TO_ISERDES(07) OR INC_TO_ISERDES_RT(07);
IODELAY_RX_DATA_07 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(07),
IDATAIN => DATA_RX_BUF(07),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_07,
INC => RX_DATA_INC_07,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_08 <= ICE_DELAY OR ICE_TO_ISERDES(08) OR ICE_TO_ISERDES_RT(08);
RX_DATA_INC_08 <= INC_DELAY OR INC_TO_ISERDES(08) OR INC_TO_ISERDES_RT(08);
IODELAY_RX_DATA_08 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(08),
IDATAIN => DATA_RX_BUF(08),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_08,
INC => RX_DATA_INC_08,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_09 <= ICE_DELAY OR ICE_TO_ISERDES(09) OR ICE_TO_ISERDES_RT(09);
RX_DATA_INC_09 <= INC_DELAY OR INC_TO_ISERDES(09) OR INC_TO_ISERDES_RT(09);
IODELAY_RX_DATA_09 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
HIGH_PERFORMANCE_MODE => "TRUE"
)
PORT MAP (
DATAOUT => DATA_RX_IDLY(09),
IDATAIN => DATA_RX_BUF(09),
ODATAIN => '0',
DATAIN => '0',
T => '1',
CE => RX_DATA_CE_09,
INC => RX_DATA_INC_09,
C => RXCLKDIV_TEMP,
RST => RX_DATA_RESET);
RX_DATA_CE_10 <= ICE_DELAY OR ICE_TO_ISERDES(10) OR ICE_TO_ISERDES_RT(10);
RX_DATA_INC_10 <= INC_DELAY OR INC_TO_ISERDES(10) OR INC_TO_ISERDES_RT(10);
IODELAY_RX_DATA_10 : IODELAY
GENERIC MAP(
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
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