📄 ddr_6to1_16chan_rt_rx.vhd
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MONITOR_TO_RT <= DATA_FROM_ISERDES_MON(71 DOWNTO 66);
INC_TO_ISERDES_RT <= "0000" & INC_DATABUS & "00000000000";
ICE_TO_ISERDES_RT <= "0000" & ICE_DATABUS & "00000000000";
INC_TO_MONITOR_RT <= "0000" & INC_MONITOR & "00000000000";
ICE_TO_MONITOR_RT <= "0000" & ICE_MONITOR & "00000000000";
WHEN "1100" =>
DATA_TO_RT <= DATA_FROM_ISERDES_TEMP(77 DOWNTO 72);
MONITOR_TO_RT <= DATA_FROM_ISERDES_MON(77 DOWNTO 72);
INC_TO_ISERDES_RT <= "000" & INC_DATABUS & "000000000000";
ICE_TO_ISERDES_RT <= "000" & ICE_DATABUS & "000000000000";
INC_TO_MONITOR_RT <= "000" & INC_MONITOR & "000000000000";
ICE_TO_MONITOR_RT <= "000" & ICE_MONITOR & "000000000000";
WHEN "1101" =>
DATA_TO_RT <= DATA_FROM_ISERDES_TEMP(83 DOWNTO 78);
MONITOR_TO_RT <= DATA_FROM_ISERDES_MON(83 DOWNTO 78);
INC_TO_ISERDES_RT <= "00" & INC_DATABUS & "0000000000000";
ICE_TO_ISERDES_RT <= "00" & ICE_DATABUS & "0000000000000";
INC_TO_MONITOR_RT <= "00" & INC_MONITOR & "0000000000000";
ICE_TO_MONITOR_RT <= "00" & ICE_MONITOR & "0000000000000";
WHEN "1110" =>
DATA_TO_RT <= DATA_FROM_ISERDES_TEMP(89 DOWNTO 84);
MONITOR_TO_RT <= DATA_FROM_ISERDES_MON(89 DOWNTO 84);
INC_TO_ISERDES_RT <= '0' & INC_DATABUS & "00000000000000";
ICE_TO_ISERDES_RT <= '0' & ICE_DATABUS & "00000000000000";
INC_TO_MONITOR_RT <= '0' & INC_MONITOR & "00000000000000";
ICE_TO_MONITOR_RT <= '0' & ICE_MONITOR & "00000000000000";
WHEN "1111" =>
DATA_TO_RT <= DATA_FROM_ISERDES_TEMP(95 DOWNTO 90);
MONITOR_TO_RT <= DATA_FROM_ISERDES_MON(95 DOWNTO 90);
INC_TO_ISERDES_RT <= INC_DATABUS & "000000000000000";
ICE_TO_ISERDES_RT <= ICE_DATABUS & "000000000000000";
INC_TO_MONITOR_RT <= INC_MONITOR & "000000000000000";
ICE_TO_MONITOR_RT <= ICE_MONITOR & "000000000000000";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
--SHORTEN EACH EXTERNAL INC AND DEC PULSE TO ONE RXCLKDIV CYCLE
PROCESS (RXCLKDIV_TEMP)
BEGIN
IF (RXCLKDIV_TEMP'EVENT AND RXCLKDIV_TEMP = '1') THEN
INC_CAPTURE(0) <= INC_PAD; -- ASYNCHRONOUS ENTRY POINT
DEC_CAPTURE(0) <= DEC_PAD;
BITSLIP_CAPTURE(0) <= BITSLIP_PAD;
FOR I IN 0 TO 3 - 1 LOOP
INC_CAPTURE(I + 1) <= INC_CAPTURE(I); -- METASTABLE FLIP-FLOPS
DEC_CAPTURE(I + 1) <= DEC_CAPTURE(I);
BITSLIP_CAPTURE(I + 1) <= BITSLIP_CAPTURE(I);
END LOOP;
INC_PULSE <= INC_CAPTURE(2) AND NOT INC_CAPTURE(3);
-- STABLE, SINGLE PULSE
DEC_PULSE <= DEC_CAPTURE(2) AND NOT DEC_CAPTURE(3);
BITSLIP_PULSE <= BITSLIP_CAPTURE(2) AND NOT BITSLIP_CAPTURE(3);
END IF;
END PROCESS;
--KEEP TRACK OF CURRENT TAP SETTING OF IDELAY IN DATA PATH OF CHANNELS 0-15
TEMP_TAP_RST_00 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_00 <= ICE_DELAY OR ICE_TO_ISERDES(00) OR ICE_TO_ISERDES_RT(00);
TEMP_TAP_UD_00 <= INC_DELAY OR INC_TO_ISERDES(00) OR INC_TO_ISERDES_RT(00);
TAP_COUNTER_00 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_00,
count => TEMP_TAP_CNT_00,
ud => TEMP_TAP_UD_00,
counter_value => TAP_00);
TEMP_TAP_RST_01 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_01 <= ICE_DELAY OR ICE_TO_ISERDES(01) OR ICE_TO_ISERDES_RT(01);
TEMP_TAP_UD_01 <= INC_DELAY OR INC_TO_ISERDES(01) OR INC_TO_ISERDES_RT(01);
TAP_COUNTER_01 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_01,
count => TEMP_TAP_CNT_01,
ud => TEMP_TAP_UD_01,
counter_value => TAP_01);
TEMP_TAP_RST_02 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_02 <= ICE_DELAY OR ICE_TO_ISERDES(02) OR ICE_TO_ISERDES_RT(02);
TEMP_TAP_UD_02 <= INC_DELAY OR INC_TO_ISERDES(02) OR INC_TO_ISERDES_RT(02);
TAP_COUNTER_02 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_02,
count => TEMP_TAP_CNT_02,
ud => TEMP_TAP_UD_02,
counter_value => TAP_02);
TEMP_TAP_RST_03 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_03 <= ICE_DELAY OR ICE_TO_ISERDES(03) OR ICE_TO_ISERDES_RT(03);
TEMP_TAP_UD_03 <= INC_DELAY OR INC_TO_ISERDES(03) OR INC_TO_ISERDES_RT(03);
TAP_COUNTER_03 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_03,
count => TEMP_TAP_CNT_03,
ud => TEMP_TAP_UD_03,
counter_value => TAP_03);
TEMP_TAP_RST_04 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_04 <= ICE_DELAY OR ICE_TO_ISERDES(04) OR ICE_TO_ISERDES_RT(04);
TEMP_TAP_UD_04 <= INC_DELAY OR INC_TO_ISERDES(04) OR INC_TO_ISERDES_RT(04);
TAP_COUNTER_04 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_04,
count => TEMP_TAP_CNT_04,
ud => TEMP_TAP_UD_04,
counter_value => TAP_04);
TEMP_TAP_RST_05 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_05 <= ICE_DELAY OR ICE_TO_ISERDES(05) OR ICE_TO_ISERDES_RT(05);
TEMP_TAP_UD_05 <= INC_DELAY OR INC_TO_ISERDES(05) OR INC_TO_ISERDES_RT(05);
TAP_COUNTER_05 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_05,
count => TEMP_TAP_CNT_05,
ud => TEMP_TAP_UD_05,
counter_value => TAP_05);
TEMP_TAP_RST_06 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_06 <= ICE_DELAY OR ICE_TO_ISERDES(06) OR ICE_TO_ISERDES_RT(06);
TEMP_TAP_UD_06 <= INC_DELAY OR INC_TO_ISERDES(06) OR INC_TO_ISERDES_RT(06);
TAP_COUNTER_06 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_06,
count => TEMP_TAP_CNT_06,
ud => TEMP_TAP_UD_06,
counter_value => TAP_06);
TEMP_TAP_RST_07 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_07 <= ICE_DELAY OR ICE_TO_ISERDES(07) OR ICE_TO_ISERDES_RT(07);
TEMP_TAP_UD_07 <= INC_DELAY OR INC_TO_ISERDES(07) OR INC_TO_ISERDES_RT(07);
TAP_COUNTER_07 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_07,
count => TEMP_TAP_CNT_07,
ud => TEMP_TAP_UD_07,
counter_value => TAP_07);
TEMP_TAP_RST_08 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_08 <= ICE_DELAY OR ICE_TO_ISERDES(08) OR ICE_TO_ISERDES_RT(08);
TEMP_TAP_UD_08 <= INC_DELAY OR INC_TO_ISERDES(08) OR INC_TO_ISERDES_RT(08);
TAP_COUNTER_08 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_08,
count => TEMP_TAP_CNT_08,
ud => TEMP_TAP_UD_08,
counter_value => TAP_08);
TEMP_TAP_RST_09 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_09 <= ICE_DELAY OR ICE_TO_ISERDES(09) OR ICE_TO_ISERDES_RT(09);
TEMP_TAP_UD_09 <= INC_DELAY OR INC_TO_ISERDES(09) OR INC_TO_ISERDES_RT(09);
TAP_COUNTER_09 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_09,
count => TEMP_TAP_CNT_09,
ud => TEMP_TAP_UD_09,
counter_value => TAP_09);
TEMP_TAP_RST_10 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_10 <= ICE_DELAY OR ICE_TO_ISERDES(10) OR ICE_TO_ISERDES_RT(10);
TEMP_TAP_UD_10 <= INC_DELAY OR INC_TO_ISERDES(10) OR INC_TO_ISERDES_RT(10);
TAP_COUNTER_10 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_10,
count => TEMP_TAP_CNT_10,
ud => TEMP_TAP_UD_10,
counter_value => TAP_10);
TEMP_TAP_RST_11 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_11 <= ICE_DELAY OR ICE_TO_ISERDES(11) OR ICE_TO_ISERDES_RT(11);
TEMP_TAP_UD_11 <= INC_DELAY OR INC_TO_ISERDES(11) OR INC_TO_ISERDES_RT(11);
TAP_COUNTER_11 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_11,
count => TEMP_TAP_CNT_11,
ud => TEMP_TAP_UD_11,
counter_value => TAP_11);
TEMP_TAP_RST_12 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_12 <= ICE_DELAY OR ICE_TO_ISERDES(12) OR ICE_TO_ISERDES_RT(12);
TEMP_TAP_UD_12 <= INC_DELAY OR INC_TO_ISERDES(12) OR INC_TO_ISERDES_RT(12);
TAP_COUNTER_12 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_12,
count => TEMP_TAP_CNT_12,
ud => TEMP_TAP_UD_12,
counter_value => TAP_12);
TEMP_TAP_RST_13 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_13 <= ICE_DELAY OR ICE_TO_ISERDES(13) OR ICE_TO_ISERDES_RT(13);
TEMP_TAP_UD_13 <= INC_DELAY OR INC_TO_ISERDES(13) OR INC_TO_ISERDES_RT(13);
TAP_COUNTER_13 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_13,
count => TEMP_TAP_CNT_13,
ud => TEMP_TAP_UD_13,
counter_value => TAP_13);
TEMP_TAP_RST_14 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_14 <= ICE_DELAY OR ICE_TO_ISERDES(14) OR ICE_TO_ISERDES_RT(14);
TEMP_TAP_UD_14 <= INC_DELAY OR INC_TO_ISERDES(14) OR INC_TO_ISERDES_RT(14);
TAP_COUNTER_14 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_14,
count => TEMP_TAP_CNT_14,
ud => TEMP_TAP_UD_14,
counter_value => TAP_14);
TEMP_TAP_RST_15 <= IDLY_RESET OR RESET;
TEMP_TAP_CNT_15 <= ICE_DELAY OR ICE_TO_ISERDES(15) OR ICE_TO_ISERDES_RT(15);
TEMP_TAP_UD_15 <= INC_DELAY OR INC_TO_ISERDES(15) OR INC_TO_ISERDES_RT(15);
TAP_COUNTER_15 : COUNT_TO_64
PORT MAP (
clk => RXCLKDIV_TEMP,
rst => TEMP_TAP_RST_15,
count => TEMP_TAP_CNT_15,
ud => TEMP_TAP_UD_15,
counter_value => TAP_15);
--CIRCUIT TO PRODUCE RESET DELAYED BY 20 CYCLES FOR BIT_ALIGN_MACHINE
PROCESS (RXCLKDIV_TEMP)
BEGIN
IF (RXCLKDIV_TEMP'EVENT AND RXCLKDIV_TEMP = '1') THEN
RESET_SM(0) <= RESET;
FOR K IN 0 TO 20 - 1 LOOP
RESET_SM(K + 1) <= RESET_SM(K);
END LOOP;
END IF;
END PROCESS;
--DATA INPUT BUFFERS WITH DUAL OUTPUTS (ONE INVERTED AND ONE NOT INVERTED)
RX_DATA_IN_00 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(00),
OB => DATA_RX_BUF_MON(00),
I => DATA_RX_P(00),
IB => DATA_RX_N(00));
RX_DATA_IN_01 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(01),
OB => DATA_RX_BUF_MON(01),
I => DATA_RX_P(01),
IB => DATA_RX_N(01));
RX_DATA_IN_02 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(02),
OB => DATA_RX_BUF_MON(02),
I => DATA_RX_P(02),
IB => DATA_RX_N(02));
RX_DATA_IN_03 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(03),
OB => DATA_RX_BUF_MON(03),
I => DATA_RX_P(03),
IB => DATA_RX_N(03));
RX_DATA_IN_04 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(04),
OB => DATA_RX_BUF_MON(04),
I => DATA_RX_P(04),
IB => DATA_RX_N(04));
RX_DATA_IN_05 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(05),
OB => DATA_RX_BUF_MON(05),
I => DATA_RX_P(05),
IB => DATA_RX_N(05));
RX_DATA_IN_06 : IBUFDS_DIFF_OUT
GENERIC MAP(
IOSTANDARD =>"LVDS_25")
PORT MAP (
O => DATA_RX_BUF(06),
OB => DATA_RX_BUF_MON(06),
I => DATA_RX_P(06),
IB => DATA_RX_N(06));
RX_DATA_IN_07 : IBUFDS_DIFF_OUT
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