📄 ddr_6to1_16chan_rt_rx.vhd
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--/////////////////////////////////////////////////////////////////////////////
--
-- File Name: DDR_6TO1_16CHAN_RT_RX.vhd
-- Version: 1.0
-- Date: 08/07/06
-- Model: XAPP860 LVDS Receiver Module
--
-- Company: Xilinx, Inc.
-- Contributor: APD Applications Group
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2006 Xilinx, Inc.
-- All rights reserved.
--
--/////////////////////////////////////////////////////////////////////////////
--
-- Summary:
--
-- The DDR_6TO1_16CHAN_RT_RX module contains all logic in the XAPP860 LVDS Receiver,
-- including 16 channels of LVDS data, one channel of LVDS clock, an initial clock/data
-- alignment algorithm, a real-time clock/data alignment algorithm, a control circuit to share the alignment machines among
-- all 16 data channels, and tap counters that keep track of the IDELAY tap
-- setting of all data channels.
--
------------------------------------------------------------------
----
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
ENTITY DDR_6TO1_16CHAN_RT_RX IS
PORT (
DATA_RX_P : IN std_logic_vector(15 DOWNTO 0); -- SERIAL SIDE RX DATA (P)
DATA_RX_N : IN std_logic_vector(15 DOWNTO 0); -- SERIAL SIDE RX DATA (N)
CLOCK_RX_P : IN std_logic; -- FORWARDED CLOCK FROM TX (P)
CLOCK_RX_N : IN std_logic; -- FORWARDED CLOCK FROM TX (N)
INC_PAD : IN std_logic; -- MANUAL INCREMENT TO DATA DELAY
DEC_PAD : IN std_logic; -- MANUAL DECREMENT TO DATA DELAY
DATA_FROM_ISERDES : OUT std_logic_vector(95 DOWNTO 0);
-- PARALLEL SIDE RX DATA
RESET : IN std_logic; -- RX DOMAIN RESET
IDLY_RESET : IN std_logic; -- IDELAY TAP RESET
IDELAYCTRL_RESET : IN std_logic; -- IDELAYCTRL CIRCUIT RESET
BITSLIP_PAD : IN std_logic; -- MANUAL BITSLIP TO DATA
CLK200 : IN std_logic; -- 200 MHZ REFERENCE CLOCK TO IDELAYCTRL
TAP_00 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_01 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_02 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_03 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_04 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_05 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_06 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_07 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_08 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_09 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_10 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_11 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_12 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_13 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_14 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_15 : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
TAP_CLK : OUT std_logic_vector(5 DOWNTO 0);
-- IDELAY TAP COUNT ON CLK CHANNEL (0-63)
TRAINING_DONE : OUT std_logic; -- ALIGNMENT OF ALL CHANNELS COMPLETE
RXCLK : OUT std_logic;
-- FORWARDED CLOCK FROM TX (BUFIO OUTPUT)
RXCLKDIV : OUT std_logic;
-- PARALLEL SIDE RX CLOCK (DIVIDED FROM RXCLK)
IDELAY_READY : OUT std_logic;
-- FLAG INDICATING THAT IDELAYCTRL IS LOCKED
RT_MANUAL_DISABLE : IN std_logic);
-- DISABLE REAL TIME WINDOW MONITORING
END DDR_6TO1_16CHAN_RT_RX;
ARCHITECTURE translated OF DDR_6TO1_16CHAN_RT_RX IS
COMPONENT COUNT_TO_64
PORT (
clk : IN std_logic;
rst : IN std_logic;
count : IN std_logic;
ud : IN std_logic;
counter_value : OUT std_logic_vector(5 DOWNTO 0));
END COMPONENT;
COMPONENT BIT_ALIGN_MACHINE
PORT (
RXCLKDIV : IN std_logic;
RXDATA : IN std_logic_vector(5 DOWNTO 0);
RST : IN std_logic;
USE_BITSLIP : IN std_logic;
SAP : IN std_logic;
INC : OUT std_logic;
ICE : OUT std_logic;
BITSLIP : OUT std_logic;
DATA_ALIGNED : OUT std_logic);
END COMPONENT;
COMPONENT RESOURCE_SHARING_CONTROL
PORT (
CHAN_SEL : OUT std_logic_vector(3 DOWNTO 0);
ALL_CHANNELS_ALIGNED : OUT std_logic;
DATA_ALIGNED : IN std_logic;
START_ALIGN : OUT std_logic;
CLK : IN std_logic;
RST : IN std_logic;
REPEAT_PROC : IN std_logic);
END COMPONENT;
COMPONENT RT_WINDOW_MONITOR
PORT (
CLOCK : IN std_logic;
RESET : IN std_logic;
TRAINING_DONE : IN std_logic;
START : IN std_logic;
DATA_MASTER : IN std_logic_vector(5 DOWNTO 0);
DATA_MONITOR : IN std_logic_vector(5 DOWNTO 0);
INC_MONITOR : OUT std_logic;
ICE_MONITOR : OUT std_logic;
INC_DATABUS : OUT std_logic;
ICE_DATABUS : OUT std_logic;
DATA_ALIGNED_RT : OUT std_logic);
END COMPONENT;
component IODELAY
generic(
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
HIGH_PERFORMANCE_MODE : string := "TRUE"
);
port(
DATAOUT : out std_logic;
C : in std_logic;
CE : in std_logic;
DATAIN : in std_logic;
IDATAIN : in std_logic;
INC : in std_logic;
ODATAIN : in std_logic;
RST : in std_logic;
T : in std_logic
);
end component;
component ISERDES_NODELAY
generic(
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : std_logic := '0';
INIT_Q2 : std_logic := '0';
INIT_Q3 : std_logic := '0';
INIT_Q4 : std_logic := '0';
INTERFACE_TYPE : string := "MEMORY";
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER"
);
port(
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
Q4 : out std_logic;
Q5 : out std_logic;
Q6 : out std_logic;
SHIFTOUT1 : out std_logic;
SHIFTOUT2 : out std_logic;
BITSLIP : in std_logic;
CE1 : in std_logic;
CE2 : in std_logic;
CLK : in std_logic;
CLKDIV : in std_logic;
CLKB : in std_logic;
D : in std_logic;
OCLK : in std_logic;
RST : in std_logic;
SHIFTIN1 : in std_logic;
SHIFTIN2 : in std_logic
);
end component;
SIGNAL CLOCK_RX_BUF : std_logic;
SIGNAL DATA_RX_BUF : std_logic_vector(15 DOWNTO 0);
SIGNAL DATA_RX_BUF_MON : std_logic_vector(15 DOWNTO 0);
SIGNAL DATA_RX_IDLY : std_logic_vector(15 DOWNTO 0);
SIGNAL DATA_RX_IDLY_MON : std_logic_vector(15 DOWNTO 0);
SIGNAL DATA_FROM_ISERDES_MON : std_logic_vector(95 DOWNTO 0);
SIGNAL DATA_FROM_ISERDES_TEMP : std_logic_vector(95 DOWNTO 0);
SIGNAL CLOCK_RX_ISERDES_OUT : std_logic;
SIGNAL BITSLIP_FROM_MACHINE : std_logic;
SIGNAL ICE_FROM_MACHINE : std_logic;
SIGNAL INC_FROM_MACHINE : std_logic;
SIGNAL DATA_ALIGNED : std_logic;
SIGNAL DATA_ALIGNED_RT : std_logic;
SIGNAL SHIFT1 : std_logic_vector(15 DOWNTO 0);
SIGNAL SHIFT2 : std_logic_vector(15 DOWNTO 0);
SIGNAL CHAN_SEL : std_logic_vector(3 DOWNTO 0);
SIGNAL CHAN_SEL_RT : std_logic_vector(3 DOWNTO 0);
SIGNAL INC_MONITOR : std_logic;
SIGNAL ICE_MONITOR : std_logic;
SIGNAL INC_DATABUS : std_logic;
SIGNAL ICE_DATABUS : std_logic;
SIGNAL INC_CAPTURE : std_logic_vector(3 DOWNTO 0);
SIGNAL DEC_CAPTURE : std_logic_vector(3 DOWNTO 0);
SIGNAL BITSLIP_CAPTURE : std_logic_vector(3 DOWNTO 0);
SIGNAL INC_PULSE : std_logic;
SIGNAL DEC_PULSE : std_logic;
SIGNAL BITSLIP_PULSE : std_logic;
SIGNAL RESET_SM : std_logic_vector(20 DOWNTO 0);
SIGNAL BITSLIP_TO_ISERDES : std_logic_vector(15 DOWNTO 0);
SIGNAL ICE_TO_ISERDES : std_logic_vector(15 DOWNTO 0);
SIGNAL INC_TO_ISERDES : std_logic_vector(15 DOWNTO 0);
SIGNAL ICE_TO_ISERDES_RT : std_logic_vector(15 DOWNTO 0);
SIGNAL INC_TO_ISERDES_RT : std_logic_vector(15 DOWNTO 0);
SIGNAL ICE_TO_MONITOR_RT : std_logic_vector(15 DOWNTO 0);
SIGNAL INC_TO_MONITOR_RT : std_logic_vector(15 DOWNTO 0);
SIGNAL DATA_TO_MACHINE : std_logic_vector(5 DOWNTO 0);
SIGNAL DATA_TO_RT : std_logic_vector(5 DOWNTO 0);
SIGNAL MONITOR_TO_RT : std_logic_vector(5 DOWNTO 0);
SIGNAL I : integer;
SIGNAL ICE_DELAY : std_logic;
SIGNAL INC_DELAY : std_logic;
SIGNAL START_ALIGN : std_logic;
SIGNAL START_ALIGN_RT : std_logic;
SIGNAL RXCLKDIV_TEMP, RXCLK_TEMP : std_logic;
SIGNAL BIT_ALIGN_MACHINE_RESET : std_logic;
SIGNAL RT_WINDOW_MONITOR_TRAINING: std_logic;
SIGNAL K : integer;
SIGNAL TRAINING_DONE_TEMP : std_logic;
SIGNAL RX_MON_RESET : std_logic;
SIGNAL TEMP_TAP_RST_00, TEMP_TAP_RST_01, TEMP_TAP_RST_02,
TEMP_TAP_RST_03, TEMP_TAP_RST_04, TEMP_TAP_RST_05,
TEMP_TAP_RST_06, TEMP_TAP_RST_07, TEMP_TAP_RST_08,
TEMP_TAP_RST_09, TEMP_TAP_RST_10, TEMP_TAP_RST_11,
TEMP_TAP_RST_12, TEMP_TAP_RST_13, TEMP_TAP_RST_14,
TEMP_TAP_RST_15 : std_logic;
SIGNAL TEMP_TAP_CNT_00, TEMP_TAP_CNT_01, TEMP_TAP_CNT_02,
TEMP_TAP_CNT_03, TEMP_TAP_CNT_04, TEMP_TAP_CNT_05,
TEMP_TAP_CNT_06, TEMP_TAP_CNT_07, TEMP_TAP_CNT_08,
TEMP_TAP_CNT_09, TEMP_TAP_CNT_10, TEMP_TAP_CNT_11,
TEMP_TAP_CNT_12, TEMP_TAP_CNT_13, TEMP_TAP_CNT_14,
TEMP_TAP_CNT_15 : std_logic;
SIGNAL TEMP_TAP_UD_00, TEMP_TAP_UD_01, TEMP_TAP_UD_02,
TEMP_TAP_UD_03, TEMP_TAP_UD_04, TEMP_TAP_UD_05,
TEMP_TAP_UD_06, TEMP_TAP_UD_07, TEMP_TAP_UD_08,
TEMP_TAP_UD_09, TEMP_TAP_UD_10, TEMP_TAP_UD_11,
TEMP_TAP_UD_12, TEMP_TAP_UD_13, TEMP_TAP_UD_14,
TEMP_TAP_UD_15 : std_logic;
SIGNAL RX_DATA_CE_00, RX_DATA_CE_01, RX_DATA_CE_02, RX_DATA_CE_03 : std_logic;
SIGNAL RX_DATA_CE_04, RX_DATA_CE_05, RX_DATA_CE_06, RX_DATA_CE_07 : std_logic;
SIGNAL RX_DATA_CE_08, RX_DATA_CE_09, RX_DATA_CE_10, RX_DATA_CE_11 : std_logic;
SIGNAL RX_DATA_CE_12, RX_DATA_CE_13, RX_DATA_CE_14, RX_DATA_CE_15 : std_logic;
SIGNAL RX_DATA_INC_00, RX_DATA_INC_01, RX_DATA_INC_02, RX_DATA_INC_03 : std_logic;
SIGNAL RX_DATA_INC_04, RX_DATA_INC_05, RX_DATA_INC_06, RX_DATA_INC_07 : std_logic;
SIGNAL RX_DATA_INC_08, RX_DATA_INC_09, RX_DATA_INC_10, RX_DATA_INC_11 : std_logic;
SIGNAL RX_DATA_INC_12, RX_DATA_INC_13, RX_DATA_INC_14, RX_DATA_INC_15 : std_logic;
SIGNAL RX_DATA_RESET : std_logic;
SIGNAL BITSLIP_00, BITSLIP_01, BITSLIP_02, BITSLIP_03 : std_logic;
SIGNAL BITSLIP_04, BITSLIP_05, BITSLIP_06, BITSLIP_07 : std_logic;
SIGNAL BITSLIP_08, BITSLIP_09, BITSLIP_10, BITSLIP_11 : std_logic;
SIGNAL BITSLIP_12, BITSLIP_13, BITSLIP_14, BITSLIP_15 : std_logic;
SIGNAL MON_BITSLIP_00, MON_BITSLIP_01, MON_BITSLIP_02, MON_BITSLIP_03 : std_logic;
SIGNAL MON_BITSLIP_04, MON_BITSLIP_05, MON_BITSLIP_06, MON_BITSLIP_07 : std_logic;
SIGNAL MON_BITSLIP_08, MON_BITSLIP_09, MON_BITSLIP_10, MON_BITSLIP_11 : std_logic;
SIGNAL MON_BITSLIP_12, MON_BITSLIP_13, MON_BITSLIP_14, MON_BITSLIP_15 : std_logic;
SIGNAL RX_MON_CE_00, RX_MON_CE_01, RX_MON_CE_02, RX_MON_CE_03 : std_logic;
SIGNAL RX_MON_CE_04, RX_MON_CE_05, RX_MON_CE_06, RX_MON_CE_07 : std_logic;
SIGNAL RX_MON_CE_08, RX_MON_CE_09, RX_MON_CE_10, RX_MON_CE_11 : std_logic;
SIGNAL RX_MON_CE_12, RX_MON_CE_13, RX_MON_CE_14, RX_MON_CE_15 : std_logic;
SIGNAL RX_MON_INC_00, RX_MON_INC_01, RX_MON_INC_02, RX_MON_INC_03 : std_logic;
SIGNAL RX_MON_INC_04, RX_MON_INC_05, RX_MON_INC_06, RX_MON_INC_07 : std_logic;
SIGNAL RX_MON_INC_08, RX_MON_INC_09, RX_MON_INC_10, RX_MON_INC_11 : std_logic;
SIGNAL RX_MON_INC_12, RX_MON_INC_13, RX_MON_INC_14, RX_MON_INC_15 : std_logic;
attribute DIFF_TERM : string;
attribute DIFF_TERM of RX_DATA_IN_00 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_01 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_02 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_03 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_04 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_05 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_06 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_07 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_08 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_09 : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_10 : label is "TRUE";
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