lvds_bist_top.bgn

FPGA之间的LVDS传输

Release 10.1.02 - Bitgen K.37 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '5vfx130t.nph' in environment
E:\FPGA\Xilinx\10.1\ISE.
   "lvds_bist_top" is an NCD, version 3.2, device xc5vfx130t, package ff1738,
speed -1
Opened constraints file lvds_bist_top.pcf.

Sun Jan 11 23:21:21 2009

E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:2 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g RetainConfigStatus:Yes -g ConfigFallback:Enable -g SelectMAPAbort:Enable -g BPI_page_size:1 -g OverTempPowerDown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No lvds_bist_top.ncd 

INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle".  Most
   commonly, bitgen has determined and will use a specific value instead of the
   generic command-line value of "Auto".  Alternately, this message appears if
   the same option is specified multiple times on the command-line.  In this
   case, the option listed last will be used.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 2**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| CclkPin              | Pullup**             |
+----------------------+----------------------+
| DonePin              | Pullup**             |
+----------------------+----------------------+
| HswapenPin           | Pullup*              |
+----------------------+----------------------+
| M0Pin                | Pullup**             |
+----------------------+----------------------+
| M1Pin                | Pullup**             |
+----------------------+----------------------+
| M2Pin                | Pullup**             |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| InitPin              | Pullup**             |
+----------------------+----------------------+
| CsPin                | Pullup**             |
+----------------------+----------------------+
| DinPin               | Pullup**             |
+----------------------+----------------------+
| BusyPin              | Pullup**             |
+----------------------+----------------------+
| RdWrPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| OverTempPowerDown    | Disable**            |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| Match_cycle          | NoWait               |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| Partial              | (Not Specified)*     |
+----------------------+----------------------+
| Encrypt              | No**                 |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired**         |
+----------------------+----------------------+
| ConfigFallback       | Enable**             |
+----------------------+----------------------+
| SelectMAPAbort       | Enable**             |
+----------------------+----------------------+
| RetainConfigStatus   | Yes**                |
+----------------------+----------------------+
| BPI_page_size        | 1**                  |
+----------------------+----------------------+
| BPI_1st_read_cycle   | 1*                   |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

Running DRC.
INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp u_DCM/DCM_ADV_INST,
   consult the device Data Sheet.
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_Cntl with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_00 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_01 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_10 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_02 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_11 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_03 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_12 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   u_lvds/uut_tx/OSERDES_TX_DATA_04 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR
   expects TRISTATE_WIDTH to be set 4.