coregen.cgp

FPGA之间的LVDS传输

# Date: Sun Jan 11 14:50:28 2009
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = .\tmp