icon_pro.xco

FPGA之间的LVDS传输

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#
# Xilinx Core Generator version K.37
# Date: Sun Jan 11 14:51:31 2009
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx30
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff324
SET removerpms = False
SET simulationfiles = structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET component_name=icon_pro
CSET enable_jtag_bufg=true
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
# CRC: 29d7feb8