generate_ila_pro_0.xco

FPGA之间的LVDS传输

NEWPROJECT .
SETPROJECT .
SET device=xc5vlx30
SET flowvendor=Other
SET createndf=False
SET formalverification=False
SET speedgrade=-3
SET removerpms=False
SET devicefamily=virtex5
SET asysymbol=False
SET simulationfiles=structural
SET implementationfiletype=Ngc
SET busformat=BusFormatAngleBracketNotRipped
SET designentry=VHDL
SET addpads=False
SET foundationsym=False
SET package=ff324
SET vhdlsim=True
SET verilogsim=False
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
CSET enable_trigger_output_port=false
CSET data_port_width=380
CSET match_type_9=basic
CSET match_type_8=basic
CSET match_type_16=basic
CSET match_type_7=basic
CSET match_type_15=basic
CSET exclude_from_data_storage_16=false
CSET match_type_6=basic
CSET match_type_14=basic
CSET exclude_from_data_storage_15=false
CSET match_type_5=basic
CSET match_type_13=basic
CSET exclude_from_data_storage_14=false
CSET match_type_4=basic
CSET match_type_12=basic
CSET exclude_from_data_storage_13=false
CSET match_type_3=basic
CSET match_type_11=basic
CSET exclude_from_data_storage_12=false
CSET match_type_2=basic
CSET match_type_10=basic
CSET exclude_from_data_storage_11=false
CSET match_type_1=basic
CSET exclude_from_data_storage_10=false
CSET use_rpms=true
CSET component_name=ila_pro_0
CSET data_same_as_trigger=false
CSET counter_width_16=Disabled
CSET counter_width_15=Disabled
CSET counter_width_14=Disabled
CSET counter_width_13=Disabled
CSET match_units_16=1
CSET enable_storage_qualification=true
CSET counter_width_12=Disabled
CSET match_units_15=1
CSET counter_width_11=Disabled
CSET match_units_14=1
CSET counter_width_10=Disabled
CSET match_units_13=1
CSET match_units_12=1
CSET match_units_11=1
CSET match_units_10=1
CSET number_of_trigger_ports=1
CSET match_units_9=1
CSET match_units_8=1
CSET match_units_7=1
CSET match_units_6=1
CSET match_units_5=1
CSET match_units_4=1
CSET match_units_3=1
CSET match_units_2=1
CSET match_units_1=1
CSET trigger_port_width_16=1
CSET trigger_port_width_15=1
CSET trigger_port_width_14=1
CSET trigger_port_width_13=1
CSET trigger_port_width_12=1
CSET trigger_port_width_11=1
CSET trigger_port_width_10=1
CSET exclude_from_data_storage_9=false
CSET exclude_from_data_storage_8=false
CSET exclude_from_data_storage_7=false
CSET trigger_port_width_9=1
CSET exclude_from_data_storage_6=false
CSET sample_on=Rising
CSET exclude_from_data_storage_5=false
CSET trigger_port_width_8=1
CSET exclude_from_data_storage_4=false
CSET trigger_port_width_7=1
CSET trigger_port_width_6=1
CSET max_sequence_levels=16
CSET exclude_from_data_storage_3=false
CSET trigger_port_width_5=1
CSET exclude_from_data_storage_2=false
CSET trigger_port_width_4=1
CSET exclude_from_data_storage_1=false
CSET sample_data_depth=2048
CSET trigger_port_width_3=1
CSET trigger_port_width_2=1
CSET counter_width_9=Disabled
CSET trigger_port_width_1=7
CSET counter_width_8=Disabled
CSET counter_width_7=Disabled
CSET counter_width_6=Disabled
CSET counter_width_5=Disabled
CSET counter_width_4=Disabled
CSET counter_width_3=Disabled
CSET counter_width_2=Disabled
CSET counter_width_1=Disabled
GENERATE