lvds_tx_rx_merge.drc

来自「FPGA之间的LVDS传输」· DRC 代码 · 共 246 行 · 第 1/2 页

DRC
246 行
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12
WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_05>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_14>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_06>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_15>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_07>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_08>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_MON_09>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1412 - Dangling pins on
   block:<uut_rx/ISERDES_CLOCK_RX>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_00 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_01 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_02 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_10 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_03 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_11 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_04 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_12 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_05 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_13 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_06 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_14 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_07 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_15 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_08 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uut_tx/OSERDES_TX_DATA_09 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_00>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_01>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_10>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_02>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_11>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_03>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_12>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_04>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_13>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_05>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_14>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_06>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_15>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_07>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_08>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on
   block:<uut_rx/ISERDES_RX_DATA_09>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.DRC detected 0 errors and 81 warnings.  Please see the previously displayed
individual error or warning messages for more details.
12

lvds_tx_rx_merge.drc - 源码说明

本页面展示了「FPGA之间的LVDS传输」中的 lvds_tx_rx_merge.drc 源码文件，采用 DRC 编程语言编写，共 246 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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