xlnx_auto_0.restore

FPGA之间的LVDS传输

   set iMessageDisplay 0
   if {[catch {
	   set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
	   set iMessageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
   }]} { 
	   # if we cannot get the IMessageDlgID interface then we are most likely
	   # running from command line and not in the GUI.
	   puts $sMessageCmdLine
   } else {
	   # got a good dialog singleton
	   set nTimeout 999999
	   set buttonValue [$iMessageDisplay Question "Project Navigator" $sMessageGUI $hasCancel $nTimeout]
	   if { $buttonValue == 2 } { ; # cancel
		   return 3
	   } elseif { $buttonValue == 3 } { ; # yes
		   return 1
	   } elseif { $buttonValue == 4 } { ; # no
		   return 2
	   } else { # probably timeout
		   return $defaultValue
	   }
   }
   return $defaultValue
}

# Call this proc to restore the ISE project.
proc restore { { project_dir "" } } {
   set script_file "xlnx_auto_0.restore"
   set project_file "xlnx_auto_0.ise"
   set backup_file "xlnx_auto_0.fail"
   set old_working_dir [pwd]
   # Make sure a project isn't already open.
   if {[IsProjectOpen]} {
      ERR "The project must be closed before performing this operation."
      cd $old_working_dir
      return
   }
   # If a project directory was supplied, cd into it.
   if {![IsBlank $project_dir]} {
     cd $project_dir
   }
   # capture the project directory ... it should be CWD at this point
   set project_dir [pwd]

   # before proceeding detect if lock files exist and if so ask the user what to do
   set proj_rootname [file rootname $project_file]
   set intermediate_proj_dir [file join $project_dir ${proj_rootname}_xdb]
   set proj_temp_dir [file join $intermediate_proj_dir "projtemp"]
   set repo_temp_dir [file join $proj_temp_dir $project_file]
   set new_lock_file [file join $proj_temp_dir ${project_file}.lock]
   set old_lock_file [GetProjectLockFile $project_file]
   set bLockFilesExist 0
   # see if any lock files are there
   if {[file exists $new_lock_file] || ![IsBlank "$old_lock_file" ] } {
      set bLockFilesExist 1
   }
   
   # if lock file(s) are found ask the user what to do
   if { $bLockFilesExist == 1 } { 
      set lockFileMsgGUI "The project to be restored appears to be locked. Remove Lock and continue the restore project process ?" 
      set lockFileMsgCmdLine "The project to be restored appears to be locked. Please remove the lock file \"$new_lock_file\" and try the restore process again." 
      set answer [dpm_DisplayQuestionDialog $lockFileMsgGUI $lockFileMsgCmdLine 2]
      if { $answer == 1 } {
         # remove the lock file(s) and the repo temo dir, if present
         # remove the new style lock file if it exists
         if {[file exists $new_lock_file]} {
            INFO "Removing lock file \"$new_lock_file\"."
            file delete -force $new_lock_file
         }
         # remove the old style lock file if it exists
         if {[file exists $old_lock_file]} {
            INFO "Removing lock file \"$old_lock_file\"."
            file delete -force $old_lock_file
         }
         # remove the temp proj dir if it exists
         if {[file exists $repo_temp_dir]} {
            INFO "Removing old temporary project directory \"$repo_temp_dir\"."
            file delete -force $repo_temp_dir
         }
      } else {
         # the user answered 'no' so exist without doing anything
         INFO "Exiting without restoring project."
         return
      }
   }
   
   # Backup this script because it will be overwritten the next time
   # the project is saved, which happens right after it is created!
   file copy -force "$script_file" "${script_file}.last"
   # Back up the project.
   set wasBackedUp [ BackUpProject "$project_file" "$backup_file" ]
   # Remove the project file, so that it can be recreated, since the old.
   # is presumably corrupted and can no longer be opened.
   OnFail [ RemoveProject "$project_file" ] {
      cd $old_working_dir
      return
   }

   # Open the project.
   HandleException {
      set iProjHelper [ OpenFacilProject "$project_file"]
   } "A problem occurred while creating the project \"$project_file\"."
   if {$iProjHelper == 0} {
      cd $old_working_dir
      return
   }
   INFO "Recreating project \"$project_file\"."
  set project_settings { 
     "PROP_DevFamily" "Automotive CoolRunner2"
     "PROP_DevDevice" "xa2c*"
     "PROP_DevPackage" "*"
     "PROP_DevSpeed" "-*"
     "PROP_Top_Level_Module_Type" "HDL"
     "PROP_Synthesis_Tool" "XST (VHDL/Verilog)"
     "PROP_Simulator" "Modelsim-SE Mixed"
     "PROP_PreferredLanguage" "Verilog"
     "PROP_Enable_Message_Capture" "true"
     "PROP_Enable_Message_Filtering" "false"
     "PROP_Enable_Incremental_Messaging" "false"
     }

  HandleException {
    RestoreProjectSettings $iProjHelper $project_settings 
  } "A problem occured while restoring project settings."

  set user_files {}

  HandleException {
    AddUserFiles $iProjHelper $user_files
  } "A problem occured while restoring user files."

  set imported_files {}

  set origination 2

  HandleException {
    AddImportedFiles $iProjHelper $imported_files $origination
  } "A problem occured while restoring imported files."

  set process_props { 
      "A" "" "" "" "PROP_BehavioralSimTop" "" 
      "A" "" "" "" "PROP_CPLDFitkeepio" "false" 
      "A" "" "" "" "PROP_CompxlibAbelLib" "true" 
      "A" "" "" "" "PROP_CompxlibCPLDDetLib" "true" 
      "A" "" "" "" "PROP_CompxlibOtherCompxlibOpts" "" 
      "A" "" "" "" "PROP_CompxlibOutputDir" "$XILINX/<language>/<simulator>" 
      "A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite" 
      "A" "" "" "" "PROP_CompxlibSimPrimatives" "true" 
      "A" "" "" "" "PROP_DesignName" "xlnx_auto_0" 
      "A" "" "" "" "PROP_Dummy" "dum1" 
      "A" "" "" "" "PROP_EnableWYSIWYG" "None" 
      "A" "" "" "" "PROP_Enable_Incremental_Messaging" "false" 
      "A" "" "" "" "PROP_Enable_Message_Capture" "true" 
      "A" "" "" "" "PROP_Enable_Message_Filtering" "false" 
      "A" "" "" "" "PROP_FitterReportFormat" "HTML" 
      "A" "" "" "" "PROP_FlowDebugLevel" "0" 
      "A" "" "" "" "PROP_FunctionBlockInputLimit" "38" 
      "A" "" "" "" "PROP_ImpactProjectFile" "Default" 
      "A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time" 
      "A" "" "" "" "PROP_ModelSimUseConfigName" "false" 
      "A" "" "" "" "PROP_Parse_Target" "synthesis" 
      "A" "" "" "" "PROP_PartitionCreateDelete" "" 
      "A" "" "" "" "PROP_PartitionForceSynth" "" 
      "A" "" "" "" "PROP_PlsClockEnable" "true" 
      "A" "" "" "" "PROP_PostFitSimTop" "" 
      "A" "" "" "" "PROP_PostParSimTop" "" 
      "A" "" "" "" "PROP_SimDo" "true" 
      "A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false" 
      "A" "" "" "" "PROP_SimModelOtherNetgenOpts" "" 
      "A" "" "" "" "PROP_SimModelRetainHierarchy" "true" 
      "A" "" "" "" "PROP_SimUseCustom_behav" "false" 
      "A" "" "" "" "PROP_SimUseCustom_postPar" "false" 
      "A" "" "" "" "PROP_SynthCaseImplStyle" "None" 
      "A" "" "" "" "PROP_SynthExtractMux" "Yes" 
      "A" "" "" "" "PROP_SynthFsmEncode" "Auto" 
      "A" "" "" "" "PROP_SynthOpt" "Speed" 
      "A" "" "" "" "PROP_SynthOptEffort" "Normal" 
      "A" "" "" "" "PROP_SynthResSharing" "true" 
      "A" "" "" "" "PROP_SynthTop" "" 
      "A" "" "" "" "PROP_Top_Level_Module_Type" "HDL" 
      "A" "" "" "" "PROP_UseDataGate" "true" 
      "A" "" "" "" "PROP_UseSmartGuide" "false" 
      "A" "" "" "" "PROP_UserConstraintEditorPreference" "Constraints Editor" 
      "A" "" "" "" "PROP_UserEditorCustomSetting" "" 
      "A" "" "" "" "PROP_UserEditorPreference" "ISE Text Editor" 
      "A" "" "" "" "PROP_XPowerOptInputTclScript" "" 
      "A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptOutputFile" "Default" 
      "A" "" "" "" "PROP_XPowerOptVerboseRpt" "false" 
      "A" "" "" "" "PROP_XPowerOtherXPowerOpts" "" 
      "A" "" "" "" "PROP_cpldBestFit" "false" 
      "A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source" 
      "A" "" "" "" "PROP_cpldfit_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_fitGenSimModel" "false" 
      "A" "" "" "" "PROP_hprep6_autosig" "false" 
      "A" "" "" "" "PROP_hprep6_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_ibiswriterShowAllModels" "false" 
      "A" "" "" "" "PROP_lockPinsUcfFile" "" 
      "A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_taengine_otherCmdLineOptions" "" 
      "A" "" "" "" "PROP_xcpldFitDesInit" "Low" 
      "A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32" 
      "A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true" 
      "A" "" "" "" "PROP_xcpldFitDesSlew" "Fast" 
      "A" "" "" "" "PROP_xcpldFitDesTimingCst" "true" 
      "A" "" "" "" "PROP_xcpldFitDesTriMode" "Keeper" 
      "A" "" "" "" "PROP_xcpldFitDesUnused" "Keeper" 
      "A" "" "" "" "PROP_xcpldFitDesVolt" "LVCMOS18" 
      "A" "" "" "" "PROP_xcpldFitTemplate_xpla3" "Optimize Density" 
      "A" "" "" "" "PROP_xcpldFittimRptOption" "Summary" 
      "A" "" "" "" "PROP_xcpldUseGlobalClocks" "true" 
      "A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true" 
      "A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true" 
      "A" "" "" "" "PROP_xcpldUseLocConst" "Always" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false" 
      "A" "" "" "" "PROP_xilxNgdbldMacro" "" 
      "A" "" "" "" "PROP_xilxNgdbld_AUL" "false" 
      "A" "" "" "" "PROP_xilxSynthAddIObuf" "true" 
      "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No" 
      "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes" 
      "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true" 
      "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" 
      "A" "" "" "" "PROP_xstBusDelimiter" "<>" 
      "A" "" "" "" "PROP_xstCase" "Maintain" 
      "A" "" "" "" "PROP_xstEquivRegRemoval" "true" 
      "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" 
      "A" "" "" "" "PROP_xstGenericsParameters" "" 
      "A" "" "" "" "PROP_xstHierarchySeparator" "/" 
      "A" "" "" "" "PROP_xstIniFile" "" 
      "A" "" "" "" "PROP_xstLibSearchOrder" "" 
      "A" "" "" "" "PROP_xstNetlistHierarchy" "As Optimized" 
      "A" "" "" "" "PROP_xstUseSynthConstFile" "true" 
      "A" "" "" "" "PROP_xstUserCompileList" "" 
      "A" "" "" "" "PROP_xstVeriIncludeDir_Global" "" 
      "A" "" "" "" "PROP_xstVerilog2001" "true" 
      "A" "" "" "" "PROP_xstVerilogMacros" "" 
      "A" "" "" "" "PROP_xstWorkDir" "./xst" 
      "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" 
      "A" "AutoGeneratedView" "VIEW_Post-FitPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-FitPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" 
      "B" "" "" "" "PROP_DevFamily" "Automotive CoolRunner2" 
      "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density" 
      "B" "" "" "" "PROP_ModelSimConfigName" "Default" 
      "B" "" "" "" "PROP_ModelSimDataWin" "false" 
      "B" "" "" "" "PROP_ModelSimListWin" "false" 
      "B" "" "" "" "PROP_ModelSimProcWin" "false" 
      "B" "" "" "" "PROP_ModelSimSignalWin" "true" 
      "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)" 
      "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns" 
      "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns" 
      "B" "" "" "" "PROP_ModelSimSourceWin" "false" 
      "B" "" "" "" "PROP_ModelSimStructWin" "true" 
      "B" "" "" "" "PROP_ModelSimUutInstName_postFit" "UUT" 
      "B" "" "" "" "PROP_ModelSimVarsWin" "false" 
      "B" "" "" "" "PROP_ModelSimWaveWin" "true" 
      "B" "" "" "" "PROP_SimCustom_behav" "" 
      "B" "" "" "" "PROP_SimCustom_postPar" "" 
      "B" "" "" "" "PROP_SimGenVcdFile" "false" 
      "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT" 
      "B" "" "" "" "PROP_SimSyntax" "93" 
      "B" "" "" "" "PROP_SimUseExpDeclOnly" "true" 
      "B" "" "" "" "PROP_SimUserCompileList_behav" "" 
      "B" "" "" "" "PROP_Simulator" "Modelsim-SE Mixed" 
      "B" "" "" "" "PROP_SmartGuideFileName" "_guide.ncd" 
      "B" "" "" "" "PROP_SynthConstraintsFile" "" 
      "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" 
      "B" "" "" "" "PROP_impactPort" "Auto - default" 
      "B" "" "" "" "PROP_vcom_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_vlog_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_vsim_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true" 
      "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28" 
      "B" "" "" "" "PROP_xstSafeImplement" "No" 
      "C" "" "" "" "PROP_CompxlibLang" "All" 
      "C" "" "" "" "PROP_CompxlibSimPath" "c:/Modeltech_6.1f/win32" 
      "C" "" "" "" "PROP_DevDevice" "xa2c*" 
      "C" "" "" "" "PROP_DevFamilyPMName" "acr2" 
      "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" 
      "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" 
      "D" "" "" "" "PROP_CompxlibUniSimLib" "true" 
      "D" "" "" "" "PROP_DevPackage" "*" 
      "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" 
      "E" "" "" "" "PROP_DevSpeed" "-*" 
      "E" "" "" "" "PROP_PreferredLanguage" "Verilog" 
      "F" "" "" "" "PROP_SimModelTarget" "Verilog" 
      "F" "" "" "" "PROP_tbwTestbenchTargetLang" "Verilog" 
      "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" 
      "G" "" "" "" "PROP_SimModelGenArchOnly" "false" 
      "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" 
      "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false" 
      "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" 
      "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" 
      "G" "" "" "" "PROP_SimModelRenTopLevMod" "" 
      "G" "" "" "" "PROP_bencherPostParTestbenchName" "" 
      "G" "" "" "" "PROP_netgenPostParSimModelName" "_timesim.v" 
      "G" "AutoGeneratedView" "VIEW_Fit" "" "PROP_PostParSimModelName" "_timesim.v" 
      "G" "AutoGeneratedView" "VIEW_Post-FitAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_TBWPost-FitPreSimulation" "" "PROP_tbwPostParTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostParSimModelName" "_timesim.v" 
      "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false" 
      "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default" 
      "H" "" "" "" "PROP_netgenRenameTopLevEntTo" "" 
      "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT" 
      "I" "" "" "" "PROP_SimModelRocPulseWidth" "100"}

  HandleException {
    RestoreProcessProperties $iProjHelper $process_props
  } "A problem occured while restoring process properties."

   # library names and their members
   set libraries {
   }

  HandleException {
    RestoreSourceLibraries $iProjHelper $libraries
  } "A problem occured while restoring source libraries."

   # partition names for recreation
   set partition_names {
   }

  HandleException {
    RestorePartitions $partition_names
  } "A problem occured while restoring partitions."

   # Close the facilitator project.
   CloseFacilProject $iProjHelper

   # cd into the project directory before trying to open thr project
   cd $project_dir

   set proj_file_full_path [file join $project_dir $project_file]
   INFO "Opening restored project file \"$proj_file_full_path\" ..."

   # Open the restored project in the user's client application,
   # which will either be the Projnav GUI or xtclsh.
   project open $project_file

   # Let the user know about the backed up project file.
   INFO "The project \"$project_file\" was successfully recovered and opened."
   if {$wasBackedUp} {
      INFO ""
      INFO "The original project was renamed as \"$backup_file\"."
      INFO "Please open a Technical Support WebCase at"
      INFO "www.xilinx.com/support/clearexpress/websupport.htm"
      INFO "and submit this file, along with the project source files, for evaluation."
   }
}