ddr_6to1_16chan_rt_tx.vhd

FPGA之间的LVDS传输

--/////////////////////////////////////////////////////////////////////////////
--
--    File Name:  DDR_6TO1_16CHAN_RT_TX.vhd
--      Version:  1.0
--         Date:  08/07/06
--        Model:  XAPP860 LVDS Transmitter Module
--
--      Company:  Xilinx, Inc.
--  Contributor:  APD Applications Group
--
--   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
--                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
--                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
--                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
--                APPLICATION OR STANDARD, XILINX IS MAKING NO
--                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
--                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
--                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
--                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
--                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
--                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
--                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
--                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--                PURPOSE.
--
--                (c) Copyright 2006 Xilinx, Inc.
--                All rights reserved.
--
--/////////////////////////////////////////////////////////////////////////////
-- 
-- Summary:
--
-- The DDR_6TO1_16CHAN_RT_TX module contains all components in the XAPP860 LVDS Transmitter,
-- including 16 channels of LVDS data, one channel of LVDS clock, and a multiplexer
-- that selects between a training pattern and user data.
-- 
------------------------------------------------------------------

----
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--

ENTITY DDR_6TO1_16CHAN_RT_TX IS
--	generic(
--		BLIND_MODE: INTEGER := 1
--	)
   PORT (
	------------------------------------------------------------------------------
--	--debug for post-simu
--		din: OUT std_logic_VECTOR(63 downto 0);
--		rd_en: OUT std_logic;
--		wr_en: OUT std_logic;
--		almost_empty: OUT std_logic;
--		almost_full: OUT std_logic;
--		dout: OUT std_logic_VECTOR(63 downto 0);
--		empty: OUT std_logic;
--		full: OUT std_logic;
	-------------------------------------------------------------------------------
      DATA_TX_P               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (P)
      DATA_TX_N               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (N)
      CLOCK_TX_P              : OUT std_logic;   -- FORWARDED CLOCK TO RX (P)
      CLOCK_TX_N              : OUT std_logic;   -- FORWARDED CLOCK TO RX (N)
      TXCLK                   : IN std_logic;   -- SERIAL SIDE TX CLOCK
      TXCLKDIV                : IN std_logic;   -- PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
      DATA_TX_FIFO	         : IN std_logic_vector(31 DOWNTO 0);   -- PARALLEL SIDE TX DATA
      DATA_TX_FIFO_VLD	      : IN std_logic;
      DATA_TX_FIFO_RDY	      : OUT std_logic;
      RESET                   : IN std_logic;   -- TX DOMAIN RESET
		TXCLK_USR					: IN std_logic;
      TRAINING_DONE           : IN std_logic);   -- FLAG FROM RECEIVER INDICATING ALIGNMENT
END DDR_6TO1_16CHAN_RT_TX;

ARCHITECTURE translated OF DDR_6TO1_16CHAN_RT_TX IS

	component fifo_tx 
		port (
		din: IN std_logic_VECTOR(31 downto 0);
		rd_clk: IN std_logic;
		rd_en: IN std_logic;
		rst: IN std_logic;
		wr_clk: IN std_logic;
		wr_en: IN std_logic;
		almost_empty: OUT std_logic;
		almost_full: OUT std_logic;
		dout: OUT std_logic_VECTOR(63 downto 0);
		empty: OUT std_logic;
		full: OUT std_logic);
	end component;
   SIGNAL TX_CLOCK_PREBUF          :  std_logic;   
   SIGNAL TX_DATA_PREBUF           :  std_logic_vector(16 DOWNTO 0);   
   SIGNAL DATA_TO_OSERDES_REG      :  std_logic_vector(67 DOWNTO 0);   
	SIGNAL DATA_TO_OSERDES          :  std_logic_vector(63 DOWNTO 0);   -- PARALLEL SIDE TX DATA
   SIGNAL FIFO_DATA_VALID			  :  std_logic;	   
   SIGNAL almost_full			  :  std_logic;	 --d means debug  
   SIGNAL almost_empty			  :  std_logic;	   
   SIGNAL rd_en			  :  std_logic;
	signal TRAINING_DONE_reg,TRAINING_DONE_reg2:  std_logic;
--	SIGNAL blind_timer_up	: std_logic;
--	SIGNAL blind_timer_cnt	: std_logic_vector(15 downto 0);
BEGIN
   
   --DATA SOURCE: TRAINING PAT OR PRBS	
   --IF NO FEEDBACK CONTROLS FROM RX ARE DESIRED, THE TX CAN BE SET TO SEND THE 
   --TRAINING PATTERN FOR A FIXED AMOUNT OF TIME, AFTER WHICH IT AUTOMATICALLY
   --ASSUMES THAT TRAINING IS COMPLETE AND BEGINS SENDING USER DATA.
   
	--DATA_TX_FIFO_RDY <= not almost_full_d;
	--rd_en_d <= not almost_empty_d;
		
	process(TXCLK_USR,RESET)
	begin
		if RESET='1' then
			TRAINING_DONE_reg <= '0';
			TRAINING_DONE_reg2 <= '0';
		elsIF (TXCLK_USR'EVENT AND TXCLK_USR = '1') THEN
				TRAINING_DONE_reg <= TRAINING_DONE;
				TRAINING_DONE_reg2 <= TRAINING_DONE_reg;
      END IF;
   END PROCESS;
		
	process(TXCLKDIV)
	begin
		IF (TXCLKDIV'EVENT AND TXCLKDIV = '1') THEN
				FIFO_DATA_VALID <=rd_en;
				rd_en <= not almost_empty;
      END IF;
   END PROCESS;
	
--	process(TXCLK_USR,RESET)
--	begin
--		IF(RESET = '1') THEN
--			blind_timer_cnt<= (OTHERS=>'0');
--		ELSIF (TXCLK_USR'EVENT AND TXCLK_USR = '1') THEN
--			IF (blind_timer_up='0') THEN
--				blind_timer_cnt <= blind_timer_cnt + 1;
--			END IF;
--      END IF;
--   END PROCESS;
	
--	process(TXCLK_USR,RESET)
--	begin
--		IF(RESET = '1') THEN
--			blind_timer_up<= '0';
--		ELSIF (TXCLK_USR'EVENT AND TXCLK_USR = '1') THEN
--			IF (blind_timer_cnt > 13000) THEN  --make sure it is long enough for training
--				blind_timer_up <= '1';
--			END IF;
--      END IF;
--   END PROCESS;
	
	process(TXCLK_USR)
	begin
		IF (TXCLK_USR'EVENT AND TXCLK_USR = '1') THEN
			IF(TRAINING_DONE_reg2 ='1') THEN
				DATA_TX_FIFO_RDY <= not almost_full;				
			ELSE
				DATA_TX_FIFO_RDY <= '0';
			END IF;
      END IF;
   END PROCESS;
	
	U_FIFO : fifo_tx 
		port map(
		din => DATA_TX_FIFO,
		rd_clk => TXCLKDIV,
		rd_en	=> rd_en,
		rst => RESET,
		wr_clk =>TXCLK_USR,
		wr_en =>DATA_TX_FIFO_VLD,
		almost_empty =>almost_empty,
		almost_full =>almost_full,
		dout  => DATA_TO_OSERDES,
		empty => open,
		full => open);


   PROCESS (TXCLKDIV)
   BEGIN
      IF (TXCLKDIV'EVENT AND TXCLKDIV = '1') THEN
         IF (TRAINING_DONE_reg2 = '1') THEN
				IF (FIFO_DATA_VALID = '1') THEN
					DATA_TO_OSERDES_REG <= "1111" & DATA_TO_OSERDES(63 downto 0);    -- PRBS
				ELSE
					DATA_TO_OSERDES_REG <= "0000" & DATA_TO_OSERDES(63 downto 0);
				END IF;
			ELSE
            DATA_TO_OSERDES_REG <= "10011001100110011001100110011001100110011001100110011001100110011001";    -- TRAINING PATTERN = 1001
         END IF;
      END IF;
   END PROCESS;
   
   --FORWARDED CLOCK	

   ODDR_TX_CLOCK : ODDR 
      GENERIC MAP(
         DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0', SRTYPE => "ASYNC")
      PORT MAP (
         Q => TX_CLOCK_PREBUF,
         C => TXCLK,
         CE => '1',
         D1 => '1',
         D2 => '0',
         R => '0',
         S => '0');   
   
   
   --FORWARDED CLOCK OUTPUT BUFFER

   OBUFDS_TX_CLOCK : OBUFDS_LVDSEXT_25 
      PORT MAP (
         O => CLOCK_TX_P,
         OB => CLOCK_TX_N,
         I => TX_CLOCK_PREBUF);   
   
   
   --MASTER OSERDES IN DATA PATH

   OSERDES_TX_DATA_00 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
      PORT MAP (
         OQ => TX_DATA_PREBUF(00),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(000),
         D2 => DATA_TO_OSERDES_REG(001),
         D3 => DATA_TO_OSERDES_REG(002),
         D4 => DATA_TO_OSERDES_REG(003),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   
   
   OSERDES_TX_DATA_01 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)

      PORT MAP (
         OQ => TX_DATA_PREBUF(01),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(004),
         D2 => DATA_TO_OSERDES_REG(005),
         D3 => DATA_TO_OSERDES_REG(006),
         D4 => DATA_TO_OSERDES_REG(007),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_02 : OSERDES
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)
 
      PORT MAP (
         OQ => TX_DATA_PREBUF(02),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(008),
         D2 => DATA_TO_OSERDES_REG(009),
         D3 => DATA_TO_OSERDES_REG(010),
         D4 => DATA_TO_OSERDES_REG(011),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_03 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)

      PORT MAP (
         OQ => TX_DATA_PREBUF(03),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(012),
         D2 => DATA_TO_OSERDES_REG(013),
         D3 => DATA_TO_OSERDES_REG(014),
         D4 => DATA_TO_OSERDES_REG(015),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_04 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)

      PORT MAP (
         OQ => TX_DATA_PREBUF(04),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(016),
         D2 => DATA_TO_OSERDES_REG(017),
         D3 => DATA_TO_OSERDES_REG(018),
         D4 => DATA_TO_OSERDES_REG(019),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_05 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1)

      PORT MAP (
         OQ => TX_DATA_PREBUF(05),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(020),
         D2 => DATA_TO_OSERDES_REG(021),
         D3 => DATA_TO_OSERDES_REG(022),
         D4 => DATA_TO_OSERDES_REG(023),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         SR => RESET,
         T1 => '0',
         T2 => '0',
         T3 => '0',
         T4 => '0',
         TCE => '0');   
   

   OSERDES_TX_DATA_06 : OSERDES 
     GENERIC MAP(
        DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "DDR",  DATA_WIDTH => 4, 
        INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", 
        SRVAL_OQ => '0', SRVAL_TQ => '0', TRISTATE_WIDTH => 1) 
      PORT MAP (
         OQ => TX_DATA_PREBUF(06),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         TQ => open,
         CLK => TXCLK,
         CLKDIV => TXCLKDIV,
         D1 => DATA_TO_OSERDES_REG(024),
         D2 => DATA_TO_OSERDES_REG(025),
         D3 => DATA_TO_OSERDES_REG(026),
         D4 => DATA_TO_OSERDES_REG(027),
         D5 => '0',
         D6 => '0',
         OCE => '1',
         REV => '0',