lvds_post.vhd

FPGA之间的LVDS传输

          TXCLKDIV => TXCLKDIV,
          DATA_TX_FIFO	         => DATA_TX_FIFO,  
			 DATA_TX_FIFO_VLD	      => DATA_TX_FIFO_VLD,
			 DATA_TX_FIFO_RDY	      => DATA_TX_FIFO_RDY,
          TRAINING_DONE_TX => TRAINING_DONE_TX
        );
 
   CLK200_process :process
   begin
		CLK200 <= '0';
		wait for (CLK200_period/2);
		CLK200 <= '1';
		wait for (CLK200_period/2);
   end process;
  
   TXCLK_process :process
   begin
		TXCLK <= '0';
		wait for (TXCLK_period/2);
		TXCLK <= '1';
		wait for (TXCLK_period/2);
   end process;
	
	TXCLKDIV_process :process
   begin
		TXCLKDIV <= '0';
		wait for (TXCLKDIV_period/2);
		TXCLKDIV <= '1';
		wait for (TXCLKDIV_period/2);
   end process;
	
	RXCLK_USR_process :process
   begin
		RXCLK_USR <= '0';
		wait for (RXCLK_USR_period/2);
		RXCLK_USR <= '1';
		wait for (RXCLK_USR_period/2);
   end process;
	
	TRAINING_DONE_TX <= TRAINING_DONE_RX;
	
	DATA_RX_P(0) <= TRANSPORT DATA_TX_P(0) after delay1 ;
	DATA_RX_N(0) <= TRANSPORT DATA_TX_N(0) after delay1 ;
	----------------------------------------------------
	DATA_RX_P(1) <= TRANSPORT DATA_TX_P(1) after delay2 ;
	DATA_RX_N(1) <= TRANSPORT DATA_TX_N(1) after delay2 ;
	----------------------------------------------------
	DATA_RX_P(2) <= TRANSPORT DATA_TX_P(2) after delay3 ;
	DATA_RX_N(2) <= TRANSPORT DATA_TX_N(2) after delay3 ;
	----------------------------------------------------
	DATA_RX_P(3) <= TRANSPORT DATA_TX_P(3) after delay4 ;
	DATA_RX_N(3) <= TRANSPORT DATA_TX_N(3) after delay4 ;
	----------------------------------------------------
	DATA_RX_P(4) <= TRANSPORT DATA_TX_P(4) after delay5 ;
	DATA_RX_N(4) <= TRANSPORT DATA_TX_N(4) after delay5 ;
	----------------------------------------------------
	DATA_RX_P(5) <= TRANSPORT DATA_TX_P(5) after delay6 ;
	DATA_RX_N(5) <= TRANSPORT DATA_TX_N(5) after delay6 ;
	----------------------------------------------------
	DATA_RX_P(6) <= TRANSPORT DATA_TX_P(6) after delay7 ;
	DATA_RX_N(6) <= TRANSPORT DATA_TX_N(6) after delay7 ;
	----------------------------------------------------
	DATA_RX_P(7) <= TRANSPORT DATA_TX_P(7) after delay8 ;
	DATA_RX_N(7) <= TRANSPORT DATA_TX_N(7) after delay8 ;
	----------------------------------------------------
	DATA_RX_P(8) <= TRANSPORT DATA_TX_P(8) after delay9 ;
	DATA_RX_N(8) <= TRANSPORT DATA_TX_N(8) after delay9 ;
	----------------------------------------------------
	DATA_RX_P(9) <= TRANSPORT DATA_TX_P(9) after delay10;
	DATA_RX_N(9) <= TRANSPORT DATA_TX_N(9) after delay10;
	----------------------------------------------------
	DATA_RX_P(10) <= TRANSPORT DATA_TX_P(10) after delay11 ;
	DATA_RX_N(10) <= TRANSPORT DATA_TX_N(10) after delay11 ;
	----------------------------------------------------
	DATA_RX_P(11) <= TRANSPORT DATA_TX_P(11) after delay12 ;
	DATA_RX_N(11) <= TRANSPORT DATA_TX_N(11) after delay12 ;
	----------------------------------------------------
	DATA_RX_P(12) <= TRANSPORT DATA_TX_P(12) after delay13 ;
	DATA_RX_N(12) <= TRANSPORT DATA_TX_N(12) after delay13 ;
	----------------------------------------------------
	DATA_RX_P(13) <= TRANSPORT DATA_TX_P(13) after delay14 ;
	DATA_RX_N(13) <= TRANSPORT DATA_TX_N(13) after delay14 ;
	----------------------------------------------------
	DATA_RX_P(14) <= TRANSPORT DATA_TX_P(14) after delay15 ;
	DATA_RX_N(14) <= TRANSPORT DATA_TX_N(14) after delay15 ;
	----------------------------------------------------
	DATA_RX_P(15) <= TRANSPORT DATA_TX_P(15) after delay16 ;
	DATA_RX_N(15) <= TRANSPORT DATA_TX_N(15) after delay16 ;
	----------------------------------------------------
	DATA_RX_P(16) <= TRANSPORT DATA_TX_P(16) after delay17 ;
	DATA_RX_N(16) <= TRANSPORT DATA_TX_N(16) after delay17 ;
	----------------------------------------------------
	
   
   CLOCK_RX_P <= TRANSPORT CLOCK_TX_P after 100 ns;
   CLOCK_RX_N <= TRANSPORT CLOCK_TX_N after 100 ns;
--	DATA_RX_P <= DATA_TX_P ;
--	DATA_RX_N <= DATA_TX_N ;
--   
--   CLOCK_RX_P <= CLOCK_TX_P ;
--   CLOCK_RX_N <= CLOCK_TX_N ;
   

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 1ms.
      
		wait for 5 us;
		RESET <= '0';
      IDLY_RESET <='0';
      IDELAYCTRL_RESET <='0';

      -- insert stimulus here 

      wait;
   end process;
	
	glitch_free: process(TXCLKDIV)
   begin		
      if rising_edge(TXCLKDIV) then
			TRAINING_DONE_TX_reg <= TRAINING_DONE_TX;
		end if;
   end process;
	
data_sti : process
   begin		
	wait until (RESET = '0');
	wait until (TRAINING_DONE_TX_reg = '1');
	wait for 1 us;
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"aaaaaaaaaaaaaaaa";
--		DATA_TX_FIFO_VLD<= '1';
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"5555555555555555";
--		DATA_TX_FIFO_VLD<= '0';
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"0000000000000000";
--		DATA_TX_FIFO_VLD<= '1';
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"ffffffffffffffff";
--		DATA_TX_FIFO_VLD<= '1';
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"1234567890abcdef";
--		DATA_TX_FIFO_VLD<= '0';
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"fedcba0987654321";
--		DATA_TX_FIFO_VLD<= '1';
--	wait until rising_edge(TXCLKDIV);
--		wait for (TXCLKDIV_period*0.75);
--		DATA_TX_FIFO<= x"87654321fedcba09";
--		DATA_TX_FIFO_VLD<= '0';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"1111111111111111";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"2222222222222222";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"3333333333333333";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"4444444444444444";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"5555555555555555";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"6666666666666666";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"7777777777777777";
		DATA_TX_FIFO_VLD<= '0';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"8888888888888888";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"9999999999999999";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"0000000000000000";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"aaaaaaaaaaaaaaaa";
		DATA_TX_FIFO_VLD<= '0';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"bbbbbbbbbbbbbbbb";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"cccccccccccccccc";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"dddddddddddddddd";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"eeeeeeeeeeeeeeee";
		DATA_TX_FIFO_VLD<= '1';
	wait until rising_edge(TXCLKDIV);
		wait for (TXCLKDIV_period*0.75);
		DATA_TX_FIFO<= x"ffffffffffffffff";
		DATA_TX_FIFO_VLD<= '0';
	wait;
	end process;

--debussy_debug:process
--  begin   
--    fsdbDumpfile("lvds.fsdb");
--    fsdbDumpvars(0,"lvds_post.vhd");
--    wait;
--  end process debussy_debug;

END;