lvds_post.vhd

FPGA之间的LVDS传输

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

 
ENTITY lvds_post IS
END lvds_post;
 
ARCHITECTURE behavior OF lvds_post IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT lvds_tx_rx_merge
    PORT(
------------------------------------------------------------------------------------
--		din: OUT std_logic_VECTOR(63 downto 0);
--		rd_en: OUT std_logic;
--		wr_en: OUT std_logic;
--		almost_empty: OUT std_logic;
--		almost_full: OUT std_logic;
--		dout: OUT std_logic_VECTOR(63 downto 0);
--		empty: OUT std_logic;
--		full: OUT std_logic;
------------------------------------------------------------------------------------
         DATA_RX_P : IN  std_logic_vector(16 downto 0);
         DATA_RX_N : IN  std_logic_vector(16 downto 0);
         CLOCK_RX_P : IN  std_logic;
         CLOCK_RX_N : IN  std_logic;
         INC_PAD : IN  std_logic;
         DEC_PAD : IN  std_logic;
         DATA_RX_FIFO       : OUT std_logic_vector(63 DOWNTO 0);   
			DATA_RX_FIFO_VLD    : OUT std_logic;
         RESET : IN  std_logic;
         IDLY_RESET : IN  std_logic;
         IDELAYCTRL_RESET : IN  std_logic;
         BITSLIP_PAD : IN  std_logic;
         CLK200 : IN  std_logic;
         TAP_00 : OUT  std_logic_vector(5 downto 0);
         TAP_01 : OUT  std_logic_vector(5 downto 0);
         TAP_02 : OUT  std_logic_vector(5 downto 0);
         TAP_03 : OUT  std_logic_vector(5 downto 0);
         TAP_04 : OUT  std_logic_vector(5 downto 0);
         TAP_05 : OUT  std_logic_vector(5 downto 0);
         TAP_06 : OUT  std_logic_vector(5 downto 0);
         TAP_07 : OUT  std_logic_vector(5 downto 0);
         TAP_08 : OUT  std_logic_vector(5 downto 0);
         TAP_09 : OUT  std_logic_vector(5 downto 0);
         TAP_10 : OUT  std_logic_vector(5 downto 0);
         TAP_11 : OUT  std_logic_vector(5 downto 0);
         TAP_12 : OUT  std_logic_vector(5 downto 0);
         TAP_13 : OUT  std_logic_vector(5 downto 0);
         TAP_14 : OUT  std_logic_vector(5 downto 0);
         TAP_15 : OUT  std_logic_vector(5 downto 0);
         TAP_16 : OUT  std_logic_vector(5 downto 0);
         TAP_CLK : OUT  std_logic_vector(5 downto 0);
         TRAINING_DONE_RX : OUT  std_logic;
         RXCLK : OUT  std_logic;
         RXCLK_USR : IN  std_logic;
         RXCLKDIV : OUT  std_logic;
         IDELAY_READY : OUT  std_logic;
         RT_MANUAL_DISABLE : IN  std_logic;
         DATA_TX_P : OUT  std_logic_vector(16 downto 0);
         DATA_TX_N : OUT  std_logic_vector(16 downto 0);
         CLOCK_TX_P : OUT  std_logic;
         CLOCK_TX_N : OUT  std_logic;
         TXCLK : IN  std_logic;
         TXCLKDIV : IN  std_logic;
         DATA_TX_FIFO	         : IN std_logic_vector(63 DOWNTO 0);   -- PARALLEL SIDE TX DATA
			DATA_TX_FIFO_VLD	      : IN std_logic;
			DATA_TX_FIFO_RDY	      : OUT std_logic;
         TRAINING_DONE_TX : IN  std_logic
        );
    END COMPONENT;
    
------------------------------------------------------------------------------------
--	signal	din:  std_logic_VECTOR(63 downto 0);
--	signal	rd_en: std_logic;
--	signal	wr_en:  std_logic;
--	signal	almost_empty:  std_logic;
--	signal	almost_full:  std_logic;
--	signal	dout:  std_logic_VECTOR(63 downto 0);
--	signal	empty:  std_logic;
--	signal	full:  std_logic;
------------------------------------------------------------------------------------
   --Inputs
   signal DATA_RX_P : std_logic_vector(16 downto 0) := (others => '1');
   signal DATA_RX_N : std_logic_vector(16 downto 0) := (others => '0');
   signal CLOCK_RX_P : std_logic := '1';
   signal CLOCK_RX_N : std_logic := '0';
   signal INC_PAD : std_logic := '0';
   signal DEC_PAD : std_logic := '0';
   signal RESET : std_logic := '1';
   signal IDLY_RESET : std_logic := '1';
   signal IDELAYCTRL_RESET : std_logic := '1';
   signal BITSLIP_PAD : std_logic := '0';
   signal CLK200 : std_logic := '0';
   signal RT_MANUAL_DISABLE : std_logic := '0';
   signal TXCLK : std_logic := '0';
   signal TXCLKDIV : std_logic := '0';
   --signal DATA_TO_OSERDES : std_logic_vector(67 downto 0) := "10111000101010001011001010101011001010001001001011001011010010101100";
   signal TRAINING_DONE_TX : std_logic := '0';
   signal TRAINING_DONE_TX_reg : std_logic := '0';
	signal DATA_TX_FIFO	         : std_logic_vector(63 DOWNTO 0);   -- PARALLEL SIDE TX DATA
   signal DATA_TX_FIFO_VLD	      : std_logic:= '0';
   signal RXCLK_USR	      		: std_logic:= '0';
      	      

 	--Outputs
   --signal DATA_FROM_ISERDES : std_logic_vector(67 downto 0);
   signal TAP_00 : std_logic_vector(5 downto 0);
   signal TAP_01 : std_logic_vector(5 downto 0);
   signal TAP_02 : std_logic_vector(5 downto 0);
   signal TAP_03 : std_logic_vector(5 downto 0);
   signal TAP_04 : std_logic_vector(5 downto 0);
   signal TAP_05 : std_logic_vector(5 downto 0);
   signal TAP_06 : std_logic_vector(5 downto 0);
   signal TAP_07 : std_logic_vector(5 downto 0);
   signal TAP_08 : std_logic_vector(5 downto 0);
   signal TAP_09 : std_logic_vector(5 downto 0);
   signal TAP_10 : std_logic_vector(5 downto 0);
   signal TAP_11 : std_logic_vector(5 downto 0);
   signal TAP_12 : std_logic_vector(5 downto 0);
   signal TAP_13 : std_logic_vector(5 downto 0);
   signal TAP_14 : std_logic_vector(5 downto 0);
   signal TAP_15 : std_logic_vector(5 downto 0);
   signal TAP_16 : std_logic_vector(5 downto 0);
   signal TAP_CLK : std_logic_vector(5 downto 0);
   signal TRAINING_DONE_RX : std_logic;
   signal RXCLK : std_logic;
   signal RXCLKDIV : std_logic;
   signal IDELAY_READY : std_logic;
   signal DATA_TX_P : std_logic_vector(16 downto 0);
   signal DATA_TX_N : std_logic_vector(16 downto 0);
   signal CLOCK_TX_P : std_logic;
   signal CLOCK_TX_N : std_logic;
   signal DATA_TX_FIFO_RDY : std_logic;
	signal DATA_RX_FIFO       :  std_logic_vector(63 DOWNTO 0);   
	signal DATA_RX_FIFO_VLD    :  std_logic;
	constant CLK200_period:time := 5 ns;
	constant TXCLK_period:time := 5 ns;
	constant TXCLKDIV_period:time := 10 ns;
	constant RXCLK_USR_period:time := 8 ns;
	
--	constant delay1:time := 97 ns;
--	constant delay2:time := 96 ns;
--	constant delay3:time := 102 ns;
--	constant delay4:time := 99 ns;
--	constant delay5:time := 103 ns;
--	constant delay6:time := 101 ns;
--	constant delay7:time := 100 ns;
--	constant delay8:time := 99 ns;
--	constant delay9:time := 100 ns;
--	constant delay10:time := 96 ns;
--	constant delay11:time := 96 ns;
--	constant delay12:time := 100 ns;
--	constant delay13:time := 102 ns;
--	constant delay14:time := 100 ns;
--	constant delay15:time := 102 ns;
--	constant delay16:time := 100 ns;
--	constant delay17:time := 101 ns;
 	constant delay1:time := 100 ns;
	constant delay2:time := 100 ns;
	constant delay3:time := 100 ns;
	constant delay4:time := 100 ns;
	constant delay5:time := 100 ns;
	constant delay6:time := 100 ns;
	constant delay7:time := 100 ns;
	constant delay8:time := 100 ns;
	constant delay9:time := 100 ns;
	constant delay10:time := 100 ns;
	constant delay11:time := 100 ns;
	constant delay12:time := 100 ns;
	constant delay13:time := 100 ns;
	constant delay14:time := 100 ns;
	constant delay15:time := 100 ns;
	constant delay16:time := 100 ns;
	constant delay17:time := 100 ns;
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: lvds_tx_rx_merge PORT MAP (
		----------------------------------------------------------------------
--			din				 => din,
--			rd_en				 => rd_en,
--			wr_en				 => wr_en,
--			almost_empty	 => almost_empty,
--			almost_full		 => almost_full,
--			dout				 => dout,
--			empty				 => empty,
--			full				 => full,
	---------------------------------------------------------------------
          DATA_RX_P => DATA_RX_P,
          DATA_RX_N => DATA_RX_N,
          CLOCK_RX_P => CLOCK_RX_P,
          CLOCK_RX_N => CLOCK_RX_N,
          INC_PAD => INC_PAD,
          DEC_PAD => DEC_PAD,
          DATA_RX_FIFO       => DATA_RX_FIFO, 
			 DATA_RX_FIFO_VLD   => DATA_RX_FIFO_VLD,
          RESET => RESET,
          IDLY_RESET => IDLY_RESET,
          IDELAYCTRL_RESET => IDELAYCTRL_RESET,
          BITSLIP_PAD => BITSLIP_PAD,
          CLK200 => CLK200,
          TAP_00 => TAP_00,
          TAP_01 => TAP_01,
          TAP_02 => TAP_02,
          TAP_03 => TAP_03,
          TAP_04 => TAP_04,
          TAP_05 => TAP_05,
          TAP_06 => TAP_06,
          TAP_07 => TAP_07,
          TAP_08 => TAP_08,
          TAP_09 => TAP_09,
          TAP_10 => TAP_10,
          TAP_11 => TAP_11,
          TAP_12 => TAP_12,
          TAP_13 => TAP_13,
          TAP_14 => TAP_14,
          TAP_15 => TAP_15,
          TAP_16 => TAP_16,
          TAP_CLK => TAP_CLK,
          TRAINING_DONE_RX => TRAINING_DONE_RX,
          RXCLK => RXCLK,
          RXCLK_USR => RXCLK_USR,
          RXCLKDIV => RXCLKDIV,
          IDELAY_READY => IDELAY_READY,
          RT_MANUAL_DISABLE => RT_MANUAL_DISABLE,
          DATA_TX_P => DATA_TX_P,
          DATA_TX_N => DATA_TX_N,
          CLOCK_TX_P => CLOCK_TX_P,
          CLOCK_TX_N => CLOCK_TX_N,
          TXCLK => TXCLK,