uut_tx_wrapper.syr

FPGA之间的LVDS传输

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : uut_tx_wrapper.ngr
Top Level Output File Name         : uut_tx_wrapper
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 134

Cell Usage :
# BELS                             : 51
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 48
#      VCC                         : 1
# FlipFlops/Latches                : 97
#      FD                          : 48
#      FDS                         : 48
#      ODDR                        : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 115
#      IBUF                        : 98
#      OBUFDS_LVDSEXT_25           : 17
# Others                           : 16
#      OSERDES                     : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 5vsx50tff1136-1 


Slice Logic Utilization: 
 Number of Slice Registers:              97  out of  32640     0%  
 Number of Slice LUTs:                   49  out of  32640     0%  
    Number used as Logic:                49  out of  32640     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     97
   Number with an unused Flip Flop:       0  out of     97     0%  
   Number with an unused LUT:            48  out of     97    49%  
   Number of fully used LUT-FF pairs:    49  out of     97    50%  
   Number of unique control sets:        49

IO Utilization: 
 Number of IOs:                         134
 Number of bonded IOBs:                 134  out of    480    27%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     32     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
TXCLKDIV                           | BUFGP                  | 112   |
TXCLK                              | BUFGP                  | 17    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------------+-------+
Control Signal                     | Buffer(FF name)              | Load  |
-----------------------------------+------------------------------+-------+
N2(XST_GND:G)                      | NONE(uutt/OSERDES_TX_DATA_09)| 64    |
-----------------------------------+------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 1.099ns (Maximum Frequency: 909.918MHz)
   Minimum input arrival time before clock: 1.989ns
   Maximum output required time after clock: 2.429ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'TXCLKDIV'
  Clock period: 1.099ns (frequency: 909.918MHz)
  Total number of paths / destination ports: 96 / 96
-------------------------------------------------------------------------
Delay:               1.099ns (Levels of Logic = 0)
  Source:            uutt/DATA_TO_OSERDES_REG_90 (FF)
  Destination:       uutt/OSERDES_TX_DATA_15 (FF)
  Source Clock:      TXCLKDIV rising
  Destination Clock: TXCLKDIV rising

  Data Path: uutt/DATA_TO_OSERDES_REG_90 to uutt/OSERDES_TX_DATA_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.471   0.336  uutt/DATA_TO_OSERDES_REG_90 (uutt/DATA_TO_OSERDES_REG_90)
     OSERDES:D1                0.292          uutt/OSERDES_TX_DATA_15
    ----------------------------------------
    Total                      1.099ns (0.763ns logic, 0.336ns route)
                                       (69.4% logic, 30.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'TXCLKDIV'
  Total number of paths / destination ports: 208 / 160
-------------------------------------------------------------------------
Offset:              1.989ns (Levels of Logic = 2)
  Source:            TRAINING_DONE (PAD)
  Destination:       uutt/DATA_TO_OSERDES_REG_95 (FF)
  Destination Clock: TXCLKDIV rising

  Data Path: TRAINING_DONE to uutt/DATA_TO_OSERDES_REG_95
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            49   0.818   0.466  TRAINING_DONE_IBUF (TRAINING_DONE_IBUF)
     INV:I->O             48   0.238   0.466  uutt/DATA_TO_OSERDES<95>11_INV_0 (uutt/DATA_TO_OSERDES<11>11)
     FDS:D                    -0.018          uutt/DATA_TO_OSERDES_REG_11
    ----------------------------------------
    Total                      1.989ns (1.056ns logic, 0.933ns route)
                                       (53.1% logic, 46.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'TXCLK'
  Total number of paths / destination ports: 34 / 34
-------------------------------------------------------------------------
Offset:              2.429ns (Levels of Logic = 1)
  Source:            uutt/ODDR_TX_CLOCK (FF)
  Destination:       CLOCK_TX_N (PAD)
  Source Clock:      TXCLK rising

  Data Path: uutt/ODDR_TX_CLOCK to CLOCK_TX_N
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     ODDR:C->Q             1   0.607   0.336  uutt/ODDR_TX_CLOCK (uutt/TX_CLOCK_PREBUF)
     OBUFDS_LVDSEXT_25:I->O        1.486          uutt/OBUFDS_TX_CLOCK (CLOCK_TX_P)
    ----------------------------------------
    Total                      2.429ns (2.093ns logic, 0.336ns route)
                                       (86.2% logic, 13.8% route)

=========================================================================


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.17 secs
 
--> 

Total memory usage is 302940 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)