uut_tx_wrapper.syr

FPGA之间的LVDS传输

    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_04> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_04> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_13> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_14> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_OQ =  DDR" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_RATE_TQ =  DDR" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "DATA_WIDTH =  6" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_OQ =  0" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "INIT_TQ =  0" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SERDES_MODE =  MASTER" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_OQ =  0" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "SRVAL_TQ =  0" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
    Set user-defined property "TRISTATE_WIDTH =  1" for instance <OSERDES_TX_DATA_15> in unit <DDR_6TO1_16CHAN_RT_TX>.
Entity <DDR_6TO1_16CHAN_RT_TX> analyzed. Unit <DDR_6TO1_16CHAN_RT_TX> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <DDR_6TO1_16CHAN_RT_TX>.
    Related source file is "E:/ISEworks/LVDS/LVDS-func/DDR_6TO1_16CHAN_RT_TX.vhd".
    Found 96-bit register for signal <DATA_TO_OSERDES_REG>.
    Summary:
	inferred  96 D-type flip-flop(s).
Unit <DDR_6TO1_16CHAN_RT_TX> synthesized.


Synthesizing Unit <uut_tx_wrapper>.
    Related source file is "E:/ISEworks/LVDS/LVDS-func/uut_tx_wrapper.vhd".
Unit <uut_tx_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 96-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '5vsx50t.nph' in environment K:\Xilinx\10.1\ISE.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 96
 Flip-Flops                                            : 96

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uut_tx_wrapper> ...

Optimizing unit <DDR_6TO1_16CHAN_RT_TX> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uut_tx_wrapper, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 96
 Flip-Flops                                            : 96

=========================================================================

=========================================================================
*                           Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------