lvds_bist_top.par

FPGA之间的LVDS传输

Release 10.1.02 par K.37 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

GYB::  Sun Jan 11 23:12:22 2009

par -w -intstyle ise -ol std -t 1 lvds_bist_top_map.ncd lvds_bist_top.ncd
lvds_bist_top.pcf 


Constraints file: lvds_bist_top.pcf.
Loading device for application Rf_Device from file '5vfx130t.nph' in environment E:\FPGA\Xilinx\10.1\ISE.
   "lvds_bist_top" is an NCD, version 3.2, device xc5vfx130t, package ff1738, speed -1

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)


Device speed data version:  "ADVANCED 1.61 2008-05-28".



Device Utilization Summary:

   Number of BSCANs                          1 out of 4      25%
   Number of BUFGs                           3 out of 32      9%
   Number of BUFGCTRLs                       2 out of 32      6%
   Number of BUFIOs                          1 out of 104     1%
   Number of DCM_ADVs                        1 out of 12      8%
   Number of IDELAYCTRLs                     1 out of 28      3%
   Number of External IOBs                 146 out of 840    17%
      Number of LOCed IOBs                  40 out of 146    27%

   Number of External IOBMs                 18 out of 420     4%
      Number of LOCed IOBMs                 18 out of 18    100%

   Number of External IOBSs                 18 out of 420     4%
      Number of LOCed IOBSs                 18 out of 18    100%

   Number of IODELAYs                       18 out of 1040    1%
   Number of ISERDESs                       17 out of 1040    1%
   Number of OLOGICs                         1 out of 1040    1%
   Number of OSERDESs                       17 out of 1040    1%
   Number of RAMB18X2s                       1 out of 298     1%
   Number of RAMB36_EXPs                    25 out of 298     8%
   Number of Slice Registers              1707 out of 81920   2%
      Number used as Flip Flops           1707
      Number used as Latches                 0
      Number used as LatchThrus              0

   Number of Slice LUTS                   1404 out of 81920   1%
   Number of Slice LUT-Flip Flop pairs    2219 out of 81920   2%


Overall effort level (-ol):   Standard 
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 1 mins 46 secs 
Finished initial Timing Analysis.  REAL time: 1 mins 46 secs 

Starting Router

Phase 1: 13003 unrouted;       REAL time: 2 mins 3 secs 

Phase 2: 7970 unrouted;       REAL time: 2 mins 10 secs 

Phase 3: 1923 unrouted;       REAL time: 2 mins 34 secs 

Phase 4: 1923 unrouted; (43750)      REAL time: 3 mins 6 secs 

Phase 5: 1916 unrouted; (0)      REAL time: 3 mins 9 secs 

Phase 6: 1916 unrouted; (0)      REAL time: 3 mins 9 secs 

Phase 7: 0 unrouted; (0)      REAL time: 3 mins 34 secs 

Updating file: lvds_bist_top.ncd with current fully routed design.

Phase 8: 0 unrouted; (0)      REAL time: 3 mins 38 secs 

Phase 9: 0 unrouted; (0)      REAL time: 3 mins 39 secs 

Phase 10: 0 unrouted; (0)      REAL time: 3 mins 58 secs 

Total REAL time to Router completion: 3 mins 59 secs 
Total CPU time to Router completion: 2 mins 23 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           CLK_DELAY | BUFGCTRL_X0Y2| No   |  546 |  0.936     |  2.503      |
+---------------------+--------------+------+------+------------+-------------+
|              CLK100 | BUFGCTRL_X0Y0| No   |   99 |  0.799     |  2.503      |
+---------------------+--------------+------+------+------------+-------------+
|       RXCLKDIV_OBUF | BUFGCTRL_X0Y3| No   |  189 |  0.568     |  2.129      |
+---------------------+--------------+------+------+------------+-------------+
|    icon_control0<0> | BUFGCTRL_X0Y4| No   |  149 |  0.646     |  2.200      |
+---------------------+--------------+------+------+------------+-------------+
|u_lvds/uut_rx/RXCLK_ |              |      |      |            |             |
|                TEMP |        IO Clk| No   |   34 |  0.128     |  0.425      |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/U0/iUPDAT |              |      |      |            |             |
|               E_OUT |         Local|      |    1 |  0.000     |  0.547      |
+---------------------+--------------+------+------+------------+-------------+
|u_lvds/uut_rx/CLOCK_ |              |      |      |            |             |
|      RX_ISERDES_OUT |         Local|      |    2 |  0.000     |  2.574      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  TS_CLK_DELAY = PERIOD TIMEGRP "CLK_DELAY" | SETUP   |     0.070ns|     4.930ns|       0|           0
   5 ns HIGH 50%                            | HOLD    |     0.275ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TS_CLK100 = PERIOD TIMEGRP "CLK100" 10 ns | SETUP   |     4.627ns|     5.373ns|       0|           0
   HIGH 50%                                 | HOLD    |     0.452ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 mins 3 secs 
Total CPU time to PAR completion: 4 mins 1 secs 

Peak Memory Usage:  409 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file lvds_bist_top.ncd



PAR done!